Datasheet > XC2C64-5PC44C

XC2C64-5PC44C

更新时间： 2024-11-07 22:28:11

品牌	Logo	应用领域
赛灵思 - XILINX		电池通信设备
页数	文件大小	规格书
12页	95K
描述
This lends power savings to High-end Communication equipment and speed to battery operated devices.

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XC2C64-5PC44C 数据手册

XC2C64 CoolRunner-II CPLD

DS092 (v1.0) December 19, 2001

Advance Product Specification

Features

Description

•

Industries best 0.18 micron CMOS CPLD

The CoolRunner-II 64-macrocell device is designed for both

high performance and low power applications. This lends

power savings to high-end communication equipment and

speed to battery operated devices.

4.0 ns pin-to-pin logic delays

less than 100 µA standby current consumption

64 macrocells with up to 1,600 logic gates

Fast input registers

Slew rate control on individual outputs

LVCMOS 1.8V through 3.3V

LVTTL 3.3V

This device consists of four Function Blocks inter-con-

nected by a low power Advanced Interconnect Matrix (AIM).

The AIM feeds 40 inputs to each Function Block. The Func-

tion Blocks consist of a 40 by 56 p-term PLA and 16 macro-

cells which contain numerous configuration bits that allow

for combinational or registered modes of operation. Addi-

tionally, these registers can be globally reset or preset and

configured as a D or T flip-flop or as a D latch. There are

also multiple clock signals, both global and local product

term based, on a per macrocell basis. Output control sig-

nals include slew rate control, bus hold and open drain. An

additional Schmitt-trigger input is available on a per input

pin basis.

•

Available in multiple package styles

44-pin PLCC with 33 user I/O

44-pin VQFP with 33 user I/O

56-ball CP (0.05mm) BGA with 45 user I/O

100-pin VQFP with 64 user I/O

•

Optimized for high performance 1.8V systems

Ultra low power operation

Advanced 0.18 micron 4-metal layer Non-volatile

process

In addition to combinatorial and registered outputs, the reg-

isters may be configured as fast inputs.

Advanced system features

Quadruple enhanced security

Multi-voltage system interface

Hot pluggable

Clocking is available on a global or Function Block basis.

Three global clocks are available for all Function Blocks as

a synchronous clock source. Global clocks are additionally

used to set or preset individual macrocell registers on

power up. Local clocks are generated in specific Function

Blocks and only available to macrocell registers in that

Function Block.

IEEE1532 In-system programmable

Superior pin locking through PLA array

Input hysteresis (Schmitt trigger) on all pins

Bus hold circuitry on all user pins

IEEE standard 1149.1 boundary scan (JTAG)

Fast programming times

Excellent pin retention during design changes

High quality and reliability

Guaranteed 10,000 program/erase cycles

20 year data retention

A DualEDGE flip-flop feature is also available on a per mac-

rocell basis. This feature allows performance where it is

needed without raising the total power consumption of the

entire device.

The CoolRunner-II 64-macrocell CPLD is I/O compatible

with standard LVTTL33 and LVCMOS18, 25, and 33 volts

(see Table 1).

Refer to the CoolRunner™-II family data sheet for architec-

ture description.

Fast Zero Power Design Technology

All CoolRunner-II CPLDs employ Fast Zero Power™ (FZP),

a design technique that employs CMOS technology in both

the fabrication and design methodology. Xilinx CoolRun-

ner-II is fabricated on a 0.18 micron process technology

which is derived from leading edge FPGA product develop-

ment. CoolRunner-II design technology employs a cascade

of CMOS gates to implement sum of products instead of tra-

ditional sense amplifier methodology. Due to this FZP tech-

nology, Xilinx CoolRunner-II CPLDs achieve both high

performance and low power operation.

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS092 (v1.0) December 19, 2001

www.xilinx.com

Advance Product Specification

1-800-255-7778

12 3 4 5 6 7...12

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