Datasheet > XC2C64A-7PC44I

XC2C64A-7PC44I

更新时间： 2024-09-19 15:58:15

品牌	Logo	应用领域
赛灵思 - XILINX		时钟输入元件可编程逻辑
页数	文件大小	规格书
16页	299K
描述
Flash PLD, 7.5ns, 64-Cell, CMOS, PQCC44, 16.50 X 16.50 MM, 1.27 MM PITCH, PLASTIC, LCC-44

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XC2C64A-7PC44I 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	LCC	包装说明：	16.50 X 16.50 MM, 1.27 MM PITCH, PLASTIC, LCC-44
针数：	44	Reach Compliance Code：	not_compliant
HTS代码：	8542.39.00.01	风险等级：	5.72
其他特性：	REAL DIGITAL DESIGN TECHNOLOGY	最大时钟频率：	200 MHz
系统内可编程：	YES	JESD-30 代码：	S-PQCC-J44
JESD-609代码：	e0	JTAG BST：	YES
长度：	16.5862 mm	湿度敏感等级：	3
专用输入次数：		I/O 线路数量：	33
宏单元数：	64	端子数量：	44
最高工作温度：	85 °C	最低工作温度：	-40 °C
组织：	0 DEDICATED INPUTS, 33 I/O	输出函数：	MACROCELL
封装主体材料：	PLASTIC/EPOXY	封装代码：	QCCJ
封装等效代码：	LDCC44,.7SQ	封装形状：	SQUARE
封装形式：	CHIP CARRIER	峰值回流温度（摄氏度）：	225
电源：	1.5/3.3,1.8 V	可编程逻辑类型：	FLASH PLD
传播延迟：	7.5 ns	认证状态：	Not Qualified
座面最大高度：	4.572 mm	子类别：	Programmable Logic Devices
最大供电电压：	1.9 V	最小供电电压：	1.7 V
标称供电电压：	1.8 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn85Pb15)	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	16.5862 mm
Base Number Matches：	1

XC2C64A-7PC44I 数据手册

XC2C64A CoolRunner-II CPLD

DS311 (v1.1) August 30, 2004

Advance Product Specification

Features

Description

•

Optimized for 1.8V systems

The CoolRunner-II 64-macrocell device is designed for both

high performance and low power applications. This lends

power savings to high-end communication equipment and

high speed to battery operated devices. Due to the low

power stand-by and dynamic operation, overall system reli-

ability is improved

As fast as 4.0 ns pin-to-pin logic delays

As low as 15 µA quiescent current

Industry’s best 0.18 micron CMOS CPLD

Optimized architecture for effective logic synthesis

Multi-voltage I/O operation — 1.5V to 3.3V

This device consists of four Function Blocks inter-con-

nected by a low power Advanced Interconnect Matrix (AIM).

The AIM feeds 40 true and complement inputs to each

Function Block. The Function Blocks consist of a 40 by 56

P-term PLA and 16 macrocells which contain numerous

configuration bits that allow for combinational or registered

modes of operation.

Available in multiple package options

44-pin PLCC with 33 user I/O

44-pin VQFP with 33 user I/O

48-land QFN with 37 user I/O

56-ball CP BGA with 45 user I/O

100-pin VQFP with 64 user I/O

Pb-free available for all packages

Additionally, these registers can be globally reset or preset

and configured as a D or T flip-flop or as a D latch. There

are also multiple clock signals, both global and local product

term types, configured on a per macrocell basis. Output pin

configurations include slew rate limit, bus hold, pull-up,

open drain and programmable grounds. A Schmitt trigger

input is available on a per input pin basis. In addition to stor-

ing macrocell output states, the macrocell registers may be

configured as "direct input" registers to store signals directly

from input pins.

•

Advanced system features

Fastest in system programming

1.8V ISP using IEEE 1532 (JTAG) interface

IEEE1149.1 JTAG Boundary Scan Test

Optional Schmitt-trigger input (per pin)

I/O Banking

RealDigital™ 100% CMOS product term

generation

Flexible clocking modes

Optional DualEDGE triggered registers

Clocking is available on a global or Function Block basis.

Three global clocks are available for all Function Blocks as

a synchronous clock source. Macrocell registers can be

individually configured to power up to the zero or one state.

A global set/reset control line is also available to asynchro-

nously set or reset selected registers during operation.

Additional local clock, synchronous clock-enable, asyncho-

nous set/reset and output enable signals can be formed

using product terms on a per-macrocell or per-Function

Block basis.

Global signal options with macrocell control

Multiple global clocks with phase selection per

macrocell

Multiple global output enables

Global set/reset

Efficient control term clocks, output enables and

set/resets for each macrocell and shared across

function blocks

Advanced design security

Optional bus-hold, 3-state or weak pullup on

selected I/O pins

A DualEDGE flip-flop feature is also available on a per mac-

rocell basis. This feature allows high performance synchro-

nous operation based on lower frequency clocking to help

reduce the total power consumption of the device.

Open-drain output option for Wired-OR and LED

drive

Optional configurable grounds on unused I/Os

Mixed I/O voltages compatible with 1.5V, 1.8V,

2.5V, and 3.3V logic levels

The CoolRunner-II 64-macrocell CPLD is I/O compatible

with standard LVTTL and LVCMOS18, LVCMOS25, and

LVCMOS33 (see Table 1). This device is also 1.5V I/O com-

patible with the use of Schmitt-trigger inputs.

PLA architecture

Superior pinout retention

100% product term routability across function

block

Hot pluggable

Refer to the CoolRunner™-II family data sheet for architec-

ture description.

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS311 (v1.1) August 30, 2004

www.xilinx.com

Advance Product Specification

1-800-255-7778

12 3 4 5 6 7...16

中文翻译

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与XC2C64A-7PC44I相关器件

型号	品牌	获取价格	描述	数据表
XC2C64A-7QFG48C	XILINX	获取价格	Flash PLD, 7.5ns, 64-Cell, CMOS, 7 X 7 MM, 0.50 MM PITCH, LEAD FREE, QFN-48
XC2C64A-7QFG48I	XILINX	获取价格	暂无描述
XC2C64A-7VQ100C	XILINX	获取价格	Flash PLD, 7.5ns, 64-Cell, CMOS, PQFP100, 14 X 14 MM, 0.50 MM PITCH, VQFP-100
XC2C64A-7VQ100I	XILINX	获取价格	Flash PLD, 7.5ns, 64-Cell, CMOS, PQFP100, 14 X 14 MM, 0.50 MM PITCH, VQFP-100
XC2C64A-7VQ44C	XILINX	获取价格	Flash PLD, 7.5ns, 64-Cell, CMOS, PQFP44, 10 X 10 MM, 0.80 MM PITCH, VQFP-44
XC2C64A-7VQG100C	XILINX	获取价格	Flash PLD, 7.5ns, 64-Cell, CMOS, PQFP100, 14 X 14 MM, 0.50 MM PITCH, LEAD FREE, VQFP-100
XC2C64A-7VQG100I	XILINX	获取价格	Flash PLD, 7.5ns, 64-Cell, CMOS, PQFP100, 14 X 14 MM, 0.50 MM PITCH, LEAD FREE, VQFP-100
XC2C64A-7VQG44C	XILINX	获取价格	Flash PLD, 7.5ns, 64-Cell, CMOS, PQFP44, 10 X 10 MM, 0.80 MM PITCH, LEAD FREE, VQFP-44
XC2C64SERIES	ETC	获取价格	CoolRunner-II CPLD
XC2S100	XILINX	获取价格	Spartan-II 2.5V FPGA Family:Introduction and Ordering Information

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