5秒后页面跳转
捷配首页

Datasheet > XC2C64A-7VQG100C
XC2C64A-7VQG100C PDF预览

XC2C64A-7VQG100C

更新时间： 2024-11-02 15:58:15
品牌 Logo 应用领域
赛灵思 - XILINX 时钟输入元件可编程逻辑
页数 文件大小 规格书
16页 305K
描述
Flash PLD, 7.5ns, 64-Cell, CMOS, PQFP100, 14 X 14 MM, 0.50 MM PITCH, LEAD FREE, VQFP-100

阅读下载

中文翻译

获取价格

XC2C64A-7VQG100C 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：QFP
包装说明：TFQFP, TQFP100,.63SQ针数：100
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：12 weeks
风险等级：0.93其他特性：REAL DIGITAL DESIGN TECHNOLOGY
最大时钟频率：200 MHz系统内可编程：YES
JESD-30 代码：S-PQFP-G100JESD-609代码：e3
JTAG BST：YES长度：14 mm
湿度敏感等级：3专用输入次数：
I/O 线路数量：64宏单元数：64
端子数量：100最高工作温度：70 °C
最低工作温度：组织：0 DEDICATED INPUTS, 64 I/O
输出函数：MACROCELL封装主体材料：PLASTIC/EPOXY
封装代码：TFQFP封装等效代码：TQFP100,.63SQ
封装形状：SQUARE封装形式：FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：260电源：1.5/3.3,1.8 V
可编程逻辑类型：FLASH PLD传播延迟：7.5 ns
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：Programmable Logic Devices最大供电电压：1.9 V
最小供电电压：1.7 V标称供电电压：1.8 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：14 mmBase Number Matches：1

XC2C64A-7VQG100C 数据手册

 浏览型号XC2C64A-7VQG100C的Datasheet PDF文件第2页浏览型号XC2C64A-7VQG100C的Datasheet PDF文件第3页浏览型号XC2C64A-7VQG100C的Datasheet PDF文件第4页浏览型号XC2C64A-7VQG100C的Datasheet PDF文件第5页浏览型号XC2C64A-7VQG100C的Datasheet PDF文件第6页浏览型号XC2C64A-7VQG100C的Datasheet PDF文件第7页 
0
R
XC2C64A CoolRunner-II CPLD  
0
0
DS311 (v2.3) November 19, 2008  
Product Specification  
Features  
Description  
•
•
•
Optimized for 1.8V systems  
The CoolRunner-II 64-macrocell device is designed for both  
high performance and low power applications. This lends  
power savings to high-end communication equipment and  
high speed to battery operated devices. Due to the low  
power stand-by and dynamic operation, overall system reli-  
ability is improved.  
-
-
As fast as 4.6 ns pin-to-pin logic delays  
As low as 15 μA quiescent current  
Industry’s best 0.18 micron CMOS CPLD  
-
-
Optimized architecture for effective logic synthesis  
Multi-voltage I/O operation — 1.5V to 3.3V  
This device consists of four Function Blocks inter-connected  
by a low power Advanced Interconnect Matrix (AIM). The  
AIM feeds 40 true and complement inputs to each Function  
Block. The Function Blocks consist of a 40 by 56 P-term  
PLA and 16 macrocells which contain numerous configura-  
tion bits that allow for combinational or registered modes of  
operation.  
Available in multiple package options  
-
-
-
-
-
44-pin VQFP with 33 user I/Os  
48-land QFN with 37 user I/Os  
56-ball CP BGA with 45 user I/Os  
100-pin VQFP with 64 user I/Os  
Pb-free available for all packages  
•
Advanced system features  
Additionally, these registers can be globally reset or preset  
and configured as a D or T flip-flop or as a D latch. There  
are also multiple clock signals, both global and local product  
term types, configured on a per macrocell basis. Output pin  
configurations include slew rate limit, bus hold, pull-up,  
open drain, and programmable grounds. A Schmitt trigger  
input is available on a per input pin basis. In addition to stor-  
ing macrocell output states, the macrocell registers can be  
configured as "direct input" registers to store signals directly  
from input pins.  
-
Fastest in system programming  
1.8V ISP using IEEE 1532 (JTAG) interface  
·
-
-
-
-
-
IEEE1149.1 JTAG Boundary Scan Test  
Optional Schmitt-trigger input (per pin)  
Two separate I/O banks  
RealDigital 100% CMOS product term generation  
Flexible clocking modes  
·
Optional DualEDGE triggered registers  
-
Global signal options with macrocell control  
·
Multiple global clocks with phase selection per  
macrocell  
Clocking is available on a global or Function Block basis.  
Three global clocks are available for all Function Blocks as a  
synchronous clock source. Macrocell registers can be indi-  
vidually configured to power up to the zero or one state. A  
global set/reset control line is also available to asynchro-  
nously set or reset selected registers during operation.  
Additional local clock, synchronous clock-enable, asynchro-  
nous set/reset, and output enable signals can be formed  
using product terms on a per-macrocell or per-Function  
Block basis.  
·
·
Multiple global output enables  
Global set/reset  
-
Efficient control term clocks, output enables, and  
set/resets for each macrocell and shared across  
function blocks  
-
-
Advanced design security  
Optional bus-hold, 3-state, or weak pullup on  
selected I/O pins  
-
Open-drain output option for Wired-OR and LED  
drive  
A DualEDGE flip-flop feature is also available on a per mac-  
rocell basis. This feature allows high performance synchro-  
nous operation based on lower frequency clocking to help  
reduce the total power consumption of the device.  
-
-
Optional configurable grounds on unused I/Os  
Mixed I/O voltages compatible with 1.5V, 1.8V,  
2.5V, and 3.3V logic levels  
-
PLA architecture  
The CoolRunner-II 64-macrocell CPLD is I/O compatible  
with standard LVTTL and LVCMOS18, LVCMOS25, and  
LVCMOS33 (see Table 1). This device is also 1.5V I/O com-  
patible with the use of Schmitt-trigger inputs.  
·
Superior pinout retention  
·
100% product term routability across function  
block  
-
Hot pluggable  
Another feature that eases voltage translation is I/O bank-  
ing. Two I/O banks are available on the CoolRunner-II 64A  
macrocell device that permit easy interfacing to 3.3V, 2.5V,  
1.8V, and 1.5V devices.  
Refer to the CoolRunner™-II family data sheet for architec-  
ture description.  
© 2004–2008 Xilinx, Inc. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS311 (v2.3) November 19, 2008  
Product Specification  
www.xilinx.com  
1
1234567...16

中文翻译

下载PDF

XC2C64A-7VQG100C 替代型号

型号 品牌 替代类型 描述 数据表
XC2C64A-7VQ100C XILINX

完全替代

 Flash PLD, 7.5ns, 64-Cell, CMOS, PQFP100, 14 X 14 MM, 0.50 MM PITCH, VQFP-100

与XC2C64A-7VQG100C相关器件

型号 品牌 获取价格 描述 数据表
XC2C64A-7VQG100I XILINX

获取价格

 		Flash PLD, 7.5ns, 64-Cell, CMOS, PQFP100, 14 X 14 MM, 0.50 MM PITCH, LEAD FREE, VQFP-100
XC2C64A-7VQG44C XILINX

获取价格

 		Flash PLD, 7.5ns, 64-Cell, CMOS, PQFP44, 10 X 10 MM, 0.80 MM PITCH, LEAD FREE, VQFP-44
XC2C64SERIES ETC

获取价格

 		CoolRunner-II CPLD
XC2S100 XILINX

获取价格

 		Spartan-II 2.5V FPGA Family:Introduction and Ordering Information
XC2S100-5CS144C XILINX

获取价格

 		Spartan-II 2.5V FPGA Family:Introduction and Ordering Information
XC2S100-5CS144I XILINX

获取价格

 		Spartan-II 2.5V FPGA Family:Introduction and Ordering Information
XC2S100-5CSG144C XILINX

获取价格

 		Spartan-II FPGA Family
XC2S100-5CSG144I XILINX

获取价格

 		Spartan-II FPGA Family
XC2S100-5FG256C XILINX

获取价格

 		Spartan-II 2.5V FPGA Family:Introduction and Ordering Information
XC2S100-5FG256I XILINX

获取价格

 		Spartan-II 2.5V FPGA Family:Introduction and Ordering Information

与XC2C64A-7VQG100C相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证