5秒后页面跳转
捷配首页

Datasheet > XC2C64-5VQG44C
XC2C64-5VQG44C PDF预览

XC2C64-5VQG44C

更新时间： 2024-09-19 15:58:15
品牌 Logo 应用领域
赛灵思 - XILINX 输入元件可编程逻辑
页数 文件大小 规格书
16页 287K
描述
Flash PLD, 5ns, 64-Cell, CMOS, PQFP44, 10 X 10 MM, 0.80 MM PITCH, VQFP-44

阅读下载

中文翻译

获取价格

XC2C64-5VQG44C 技术参数

是否Rohs认证：符合生命周期：Obsolete
零件包装代码：QFP包装说明：10 X 10 MM, 0.80 MM PITCH, VQFP-44
针数：44Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.19
Is Samacsys：N其他特性：REAL DIGITAL DESIGN TECHNOLOGY
系统内可编程：YESJESD-30 代码：S-PQFP-G44
JESD-609代码：e3JTAG BST：YES
长度：10 mm湿度敏感等级：3
专用输入次数：I/O 线路数量：33
宏单元数：64端子数量：44
最高工作温度：70 °C最低工作温度：
组织：0 DEDICATED INPUTS, 33 I/O输出函数：MACROCELL
封装主体材料：PLASTIC/EPOXY封装代码：TQFP
封装等效代码：TQFP44,.47SQ,32封装形状：SQUARE
封装形式：FLATPACK, THIN PROFILE峰值回流温度（摄氏度）：260
电源：1.5/3.3,1.8 V可编程逻辑类型：FLASH PLD
传播延迟：5 ns认证状态：Not Qualified
座面最大高度：1.2 mm子类别：Programmable Logic Devices
最大供电电压：1.9 V最小供电电压：1.7 V
标称供电电压：1.8 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.8 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：10 mm
Base Number Matches：1

XC2C64-5VQG44C 数据手册

 浏览型号XC2C64-5VQG44C的Datasheet PDF文件第2页浏览型号XC2C64-5VQG44C的Datasheet PDF文件第3页浏览型号XC2C64-5VQG44C的Datasheet PDF文件第4页浏览型号XC2C64-5VQG44C的Datasheet PDF文件第5页浏览型号XC2C64-5VQG44C的Datasheet PDF文件第6页浏览型号XC2C64-5VQG44C的Datasheet PDF文件第7页 
0
R
XC2C64 CoolRunner-II CPLD  
0
0
DS092 (v3.0) November 30, 2005  
Product Specification  
·
100% product term routability across function  
block  
Note: This product is being discontinued. You cannot  
order this part after April 24, 2006. Xilinx recommends  
replacing the XC2C64 device with the XC2C64A device in  
all designs as soon as possible. The XC2C64A device is  
pin-to-pin compatible with the XC2C64 device. See  
XCN05017 for details regarding the discontinuation of the  
XC2C64 device.  
-
Hot pluggable  
Refer to the CoolRunner™-II family data sheet for architec-  
ture description.  
Description  
The CoolRunner-II 64-macrocell device is designed for both  
high performance and low power applications. This lends  
power savings to high-end communication equipment and  
high speed to battery operated devices. Due to the low  
power stand-by and dynamic operation, overall system reli-  
ability is improved  
Features  
•
•
•
Optimized for 1.8V systems  
-
-
As fast as 4.6 ns pin-to-pin logic delays  
As low as 15 µA quiescent current  
Industries best 0.18 micron CMOS CPLD  
-
-
Optimized architecture for effective logic synthesis  
Multi-voltage I/O operation — 1.5V to 3.3V  
This device consists of four Function Blocks inter-con-  
nected by a low power Advanced Interconnect Matrix (AIM).  
The AIM feeds 40 true and complement inputs to each  
Function Block. The Function Blocks consist of a 40 by 56  
P-term PLA and 16 macrocells which contain numerous  
configuration bits that allow for combinational or registered  
modes of operation.  
Available in multiple package options  
-
-
-
-
44-pin PLCC with 33 user I/O  
44-pin VQFP with 33 user I/O  
56-ball CP BGA with 45 user I/O  
100-pin VQFP with 64 user I/O  
Additionally, these registers can be globally reset or preset  
and configured as a D or T flip-flop or as a D latch. There  
are also multiple clock signals, both global and local product  
term types, configured on a per macrocell basis. Output pin  
configurations include slew rate limit, bus hold, pull-up,  
open drain and programmable grounds. A Schmitt trigger  
input is available on a per input pin basis. In addition to stor-  
ing macrocell output states, the macrocell registers may be  
configured as "direct input" registers to store signals directly  
from input pins.  
•
Advanced system features  
-
Fastest in system programming  
1.8V ISP using IEEE 1532 (JTAG) interface  
·
-
-
-
IEEE1149.1 JTAG Boundary Scan Test  
Optional Schmitt-trigger input (per pin)  
RealDigital™ 100% CMOS product term  
generation  
-
-
Flexible clocking modes  
·
Optional DualEDGE triggered registers  
Global signal options with macrocell control  
·
Multiple global clocks with phase selection per  
macrocell  
Multiple global output enables  
Global set/reset  
Clocking is available on a global or Function Block basis.  
Three global clocks are available for all Function Blocks as  
a synchronous clock source. Macrocell registers can be  
individually configured to power up to the zero or one state.  
A global set/reset control line is also available to asynchro-  
nously set or reset selected registers during operation.  
Additional local clock, synchronous clock-enable, asynchro-  
nous set/reset and output enable signals can be formed  
using product terms on a per-macrocell or per-Function  
Block basis.  
·
·
-
Efficient control term clocks, output enables and  
set/resets for each macrocell and shared across  
function blocks  
Advanced design security  
Open-drain output option for Wired-OR and LED  
drive  
Optional configurable grounds on unused I/Os  
Optional bus-hold, 3-state or weak pull-up on  
selected I/O pins  
Mixed I/O voltages compatible with 1.5V, 1.8V,  
2.5V, and 3.3V logic levels  
-
-
-
-
A DualEDGE flip-flop feature is also available on a per mac-  
rocell basis. This feature allows high performance synchro-  
nous operation based on lower frequency clocking to help  
reduce the total power consumption of the device.  
-
-
The CoolRunner-II 64-macrocell CPLD is I/O compatible  
with standard LVTTL and LVCMOS18, LVCMOS25, and  
PLA architecture  
·
Superior pinout retention  
© 2005 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS092 (v3.0) November 30, 2005  
www.xilinx.com  
1
Product Specification  
1234567...16

中文翻译

下载PDF

与XC2C64-5VQG44C相关器件

型号 品牌 获取价格 描述 数据表
XC2C64-7CP56C XILINX

获取价格

 		This lends power savings to High-end Communication equipment and speed to battery operated
XC2C64-7CP56I XILINX

获取价格

 		This lends power savings to High-end Communication equipment and speed to battery operated
XC2C64-7PC44C XILINX

获取价格

 		This lends power savings to High-end Communication equipment and speed to battery operated
XC2C64-7PC44I XILINX

获取价格

 		This lends power savings to High-end Communication equipment and speed to battery operated
XC2C64-7VQ100C XILINX

获取价格

 		This lends power savings to High-end Communication equipment and speed to battery operated
XC2C64-7VQ100I XILINX

获取价格

 		This lends power savings to High-end Communication equipment and speed to battery operated
XC2C64-7VQ44C XILINX

获取价格

 		This lends power savings to High-end Communication equipment and speed to battery operated
XC2C64-7VQ44I XILINX

获取价格

 		This lends power savings to High-end Communication equipment and speed to battery operated
XC2C64-7VQG44I XILINX

获取价格

 		Flash PLD, 7.5ns, 64-Cell, CMOS, PQFP44, 10 X 10 MM, 0.80 MM PITCH, VQFP-44
XC2C64A XILINX

获取价格

 		CoolRunner-II CPLD Family

与XC2C64-5VQG44C相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证