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XC2C64-5CP56C PDF预览

XC2C64-5CP56C

更新时间： 2024-09-18 22:28:11
品牌 Logo 应用领域
赛灵思 - XILINX 电池通信设备
页数 文件大小 规格书
12页 95K
描述
This lends power savings to High-end Communication equipment and speed to battery operated devices.

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XC2C64-5CP56C 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：6 X 6 MM, 0.50 MM PITCH, CSP-56
针数：56Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.18其他特性：REAL DIGITAL DESIGN TECHNOLOGY
系统内可编程：YESJESD-30 代码：S-PBGA-B56
JESD-609代码：e0JTAG BST：YES
长度：6 mm湿度敏感等级：3
专用输入次数：I/O 线路数量：45
宏单元数：64端子数量：56
最高工作温度：70 °C最低工作温度：
组织：0 DEDICATED INPUTS, 45 I/O输出函数：MACROCELL
封装主体材料：PLASTIC/EPOXY封装代码：LFBGA
封装等效代码：BGA56,10X10,20封装形状：SQUARE
封装形式：GRID ARRAY, LOW PROFILE, FINE PITCH峰值回流温度（摄氏度）：240
电源：1.5/3.3,1.8 V可编程逻辑类型：FLASH PLD
传播延迟：5 ns认证状态：Not Qualified
座面最大高度：1.35 mm子类别：Programmable Logic Devices
最大供电电压：1.9 V最小供电电压：1.7 V
标称供电电压：1.8 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn63Pb37)端子形式：BALL
端子节距：0.5 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：30宽度：6 mm
Base Number Matches：1

XC2C64-5CP56C 数据手册

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XC2C64 CoolRunner-II CPLD  
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DS092 (v1.0) December 19, 2001  
Advance Product Specification  
Features  
Description  
•
Industries best 0.18 micron CMOS CPLD  
The CoolRunner-II 64-macrocell device is designed for both  
high performance and low power applications. This lends  
power savings to high-end communication equipment and  
speed to battery operated devices.  
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4.0 ns pin-to-pin logic delays  
less than 100 µA standby current consumption  
64 macrocells with up to 1,600 logic gates  
Fast input registers  
Slew rate control on individual outputs  
LVCMOS 1.8V through 3.3V  
LVTTL 3.3V  
This device consists of four Function Blocks inter-con-  
nected by a low power Advanced Interconnect Matrix (AIM).  
The AIM feeds 40 inputs to each Function Block. The Func-  
tion Blocks consist of a 40 by 56 p-term PLA and 16 macro-  
cells which contain numerous configuration bits that allow  
for combinational or registered modes of operation. Addi-  
tionally, these registers can be globally reset or preset and  
configured as a D or T flip-flop or as a D latch. There are  
also multiple clock signals, both global and local product  
term based, on a per macrocell basis. Output control sig-  
nals include slew rate control, bus hold and open drain. An  
additional Schmitt-trigger input is available on a per input  
pin basis.  
•
Available in multiple package styles  
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44-pin PLCC with 33 user I/O  
44-pin VQFP with 33 user I/O  
56-ball CP (0.05mm) BGA with 45 user I/O  
100-pin VQFP with 64 user I/O  
•
•
Optimized for high performance 1.8V systems  
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Ultra low power operation  
Advanced 0.18 micron 4-metal layer Non-volatile  
process  
In addition to combinatorial and registered outputs, the reg-  
isters may be configured as fast inputs.  
Advanced system features  
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Quadruple enhanced security  
Multi-voltage system interface  
Hot pluggable  
Clocking is available on a global or Function Block basis.  
Three global clocks are available for all Function Blocks as  
a synchronous clock source. Global clocks are additionally  
used to set or preset individual macrocell registers on  
power up. Local clocks are generated in specific Function  
Blocks and only available to macrocell registers in that  
Function Block.  
IEEE1532 In-system programmable  
Superior pin locking through PLA array  
Input hysteresis (Schmitt trigger) on all pins  
Bus hold circuitry on all user pins  
IEEE standard 1149.1 boundary scan (JTAG)  
Fast programming times  
Excellent pin retention during design changes  
High quality and reliability  
Guaranteed 10,000 program/erase cycles  
20 year data retention  
A DualEDGE flip-flop feature is also available on a per mac-  
rocell basis. This feature allows performance where it is  
needed without raising the total power consumption of the  
entire device.  
The CoolRunner-II 64-macrocell CPLD is I/O compatible  
with standard LVTTL33 and LVCMOS18, 25, and 33 volts  
(see Table 1).  
Refer to the CoolRunner™-II family data sheet for architec-  
ture description.  
Fast Zero Power Design Technology  
All CoolRunner-II CPLDs employ Fast Zero Power™ (FZP),  
a design technique that employs CMOS technology in both  
the fabrication and design methodology. Xilinx CoolRun-  
ner-II is fabricated on a 0.18 micron process technology  
which is derived from leading edge FPGA product develop-  
ment. CoolRunner-II design technology employs a cascade  
of CMOS gates to implement sum of products instead of tra-  
ditional sense amplifier methodology. Due to this FZP tech-  
nology, Xilinx CoolRunner-II CPLDs achieve both high  
performance and low power operation.  
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS092 (v1.0) December 19, 2001  
www.xilinx.com  
1
Advance Product Specification  
1-800-255-7778  
1234567...12

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 		This lends power savings to High-end Communication equipment and speed to battery operated

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