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XC2C512-6FG324C PDF预览

XC2C512-6FG324C

更新时间： 2024-09-19 20:03:07
品牌 Logo 应用领域
赛灵思 - XILINX 输入元件可编程逻辑
页数 文件大小 规格书
26页 415K
描述
Flash PLD, 6ns, 512-Cell, CMOS, PBGA324, 23 X 23 MM, 1.20 MM PITCH, FBGA-324

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XC2C512-6FG324C 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：23 X 23 MM, 1.20 MM PITCH, FBGA-324针数：324
Reach Compliance Code：not_compliantHTS代码：8542.39.00.01
风险等级：5.73其他特性：YES
系统内可编程：YESJESD-30 代码：S-PBGA-B324
JESD-609代码：e0JTAG BST：YES
长度：23 mm湿度敏感等级：3
专用输入次数：I/O 线路数量：270
宏单元数：512端子数量：324
最高工作温度：70 °C最低工作温度：
组织：0 DEDICATED INPUTS, 270 I/O输出函数：MACROCELL
封装主体材料：PLASTIC/EPOXY封装代码：BGA
封装等效代码：BGA324,22X22,40封装形状：SQUARE
封装形式：GRID ARRAY峰值回流温度（摄氏度）：225
电源：1.5/3.3,1.8 V可编程逻辑类型：FLASH PLD
传播延迟：6 ns认证状态：Not Qualified
座面最大高度：2.5 mm子类别：Programmable Logic Devices
最大供电电压：1.9 V最小供电电压：1.7 V
标称供电电压：1.8 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn63Pb37)端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：30宽度：23 mm
Base Number Matches：1

XC2C512-6FG324C 数据手册

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XC2C512 CoolRunner-II CPLD  
0
0
DS096 (v2.4) October 1, 2004  
Preliminary Product Specification  
Features  
Description  
•
Optimized for 1.8V systems  
The CoolRunner-II 512-macrocell device is designed for  
both high performance and low power applications. This  
lends power savings to high-end communication equipment  
and high speed to battery operated devices. Due to the low  
power stand-by and dynamic operation, overall system reli-  
ability is improved  
-
-
As fast as 6.0 ns pin-to-pin delays  
As low as 14 µA quiescent current  
•
Industry’s best 0.18 micron CMOS CPLD  
-
-
Optimized architecture for effective logic synthesis  
Multi-voltage I/O operation — 1.5V to 3.3V  
This device consists of thirty two Function Blocks inter-con-  
nected by a low power Advanced Interconnect Matrix (AIM).  
The AIM feeds 40 true and complement inputs to each  
Function Block. The Function Blocks consist of a 40 by 56  
P-term PLA and 16 macrocells which contain numerous  
configuration bits that allow for combinational or registered  
modes of operation.  
•
•
Available in multiple package options  
-
-
-
-
208-pin PQFP with 173 user I/O  
256-ball FT (1.0mm) BGA with 212 user I/O  
324-ball FG (1.2mm) BGA with 270 user I/O  
Pb-free available for all packages  
Advanced system features  
-
Fastest in system programming  
1.8V ISP using IEEE 1532 (JTAG) interface  
Additionally, these registers can be globally reset or preset  
and configured as a D or T flip-flop or as a D latch. There  
are also multiple clock signals, both global and local product  
term types, configured on a per macrocell basis. Output pin  
configurations include slew rate limit, bus hold, pull-up,  
open drain and programmable grounds. A Schmitt-trigger  
input is available on a per input pin basis. In addition to stor-  
ing macrocell output states, the macrocell registers may be  
configured as "direct input" registers to store signals directly  
from input pins.  
·
-
-
-
IEEE1149.1 JTAG Boundary Scan Test  
Optional Schmitt-trigger input (per pin)  
Unsurpassed low power management  
·
DataGATE enable signal control  
-
-
-
Four seperate output banks  
RealDigital 100% CMOS product term generation  
Flexible clocking modes  
·
·
·
Optional DualEDGE triggered registers  
Clock divider (divide by 2,4,6,8,10,12,14,16)  
CoolCLOCK  
Clocking is available on a global or Function Block basis.  
Three global clocks are available for all Function Blocks as  
a synchronous clock source. Macrocell registers can be  
individually configured to power up to the zero or one state.  
A global set/reset control line is also available to asynchro-  
nously set or reset selected registers during operation.  
Additional local clock, synchronous clock-enable, asyncho-  
nous set/reset and output enable signals can be formed  
using product terms on a per-macrocell or per-Function  
Block basis.  
-
Global signal options with macrocell control  
·
Multiple global clocks with phase selection per  
macrocell  
·
·
Multiple global output enables  
Global set/reset  
-
-
Advanced design security  
PLA architecture  
·
·
Superior pinout retention  
100% product term routability across function  
block  
A DualEDGE flip-flop feature is also available on a per mac-  
rocell basis. This feature allows high performance synchro-  
nous operation based on lower frequency clocking to help  
reduce the total power consumption of the device.  
-
-
Open-drain output option for Wired-OR and LED  
drive  
Optional bus-hold, 3-state or weak pullup on  
selected I/O pins  
Circuitry has also been included to divide one externally  
supplied global clock (GCK2) by eight different selections.  
This yields divide by even and odd clock frequencies.  
-
-
Optional configurable grounds on unused I/Os  
Mixed I/O voltages compatible with 1.5V, 1.8V,  
2.5V, and 3.3V logic levels  
The use of the clock divide (division by 2) and DualEDGE  
flip-flop gives the resultant CoolCLOCK feature.  
·
SSTL2-1, SSTL3-1, and HSTL-1 I/O compatibility  
-
Hot Pluggable  
DataGATE is a method to selectively disable inputs of the  
CPLD that are not of interest during certain points in time.  
Refer to the CoolRunner™-II family data sheet for architec-  
ture description.  
© 2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.  
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.  
DS096 (v2.4) October 1, 2004  
www.xilinx.com  
1
Preliminary Product Specification  
1-800-255-7778  
1234567...26

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