WED2ZLRSP01S
White Electronic Designs
512K x 32/256K x 32 Dual Array
Synchronous Pipeline Burst NBL SRAM
FEATURES
DESCRIPTION
The WED2ZLRSP01S, Dual Independent Array, NBL-
SSRAM device employs high-speed, Low-Power CMOS
silicon and is fabricated using an advanced CMOS process.
WEDC’s 24Mb, Sync Burst SRAM MCP integrates two
totally independent arrays, the first organized as a 512K x
32, and the second a 256K x 32.
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Fast clock speed: 166, 150, 133, and 100MHz
Fast access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns
Fast OE# access times: 3.5ns, 3.8ns, 4.2ns, and
5.0ns
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Single +2.5V 5% power supply (VCC)
All Synchronous inputs pass through registers controlled
by a positive edge triggered, single clock input per array.
The NBL or No Bus Latency Memory provides 100% bus
utilizaton, with no loss of cycles caused by change in modal
operation (Write to Read/Read to Write). All inputs except
for Asynchronous Output Enable and Burst Mode control
are synchronized on the positive or rising edge of Clock.
Burst order control must be tied either HIGH or LOW, Write
cycles are internally self-timed, and writes are initiated on
the rising edge of clock. This feature eliminates the need
for complex off-chip write pulse generation and proved
increased timing flexibility for incoming signals.
Snooze Mode for reduced-standby power
Individual Byte Write control
Clock-controlled and registered addresses, data
I/Os and control signals
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Burst control (interleaved or linear burst)
Packaging:
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209-bump BGA package
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Low capacitive bus loading
PIN CONFIGURATION
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
Vss
A_DATb0
A_DATb1
A_DATb2
A_DATb3
A_DATb7
A_BWEb
Vcc
Vss
Vss
Vss
Vcc
Vcc
Vcc
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vcc
Vcc
Vcc
Vss
Vss
Vss
A_DATa0
A_DATa1
A_DATa2
A_DATa3
Vss
A
B
C
D
E
F
G
H
J
NC
A_ADR
A_ADR
A_ADR
A_ADR
A_ADR
NC
A_DATb4
A_ADR
Vss
A_DATb5
A_OE#
A_DATb6
A_ADV
Vcc
A_DATa4
A_BWEa
Vcc
A_DATa5
A_ZZ
A_DATa6
A_ADR
Vcc
A_DATa7
A_ADR
A_ADR
A_ADR1
A_ADR
A_ADR
A_DATd3
A_DATd7
Vss
NC
A_ADR
A_ADR
A_ADR0
A_ADR
A_ADR
NC
A_CKE#
A_GWE#
A_CS2#
A_CS1#
A_DATc1
A_DATc5
Vss
Vcc
A_CK
Vcc
Vcc
Vcc
Vcc
Vcc
Vss
Vcc
Vcc
Vcc
Vcc
Vcc
A_ADR
A_DATc0
A_DATc4
Vss
A_CS2
A_DATc2
A_DATc6
Vss
A_BWEc
A_DATc3
A_DATc7
Vss
A_BWEd
A_DATd0
A_DATd4
Vss
A_LBO#
A_DATd1
A_DATd5
Vss
A_ADR
A_DATd2
A_DATd6
Vss
Vss
Vss
Vss
Vss
K
L
Vss
B_DATb0
B_DATb4
B_ADR
Vss
B_DATb1
B_DATb5
B_OE#
B_DATb2
B_DATb6
B_ADV
Vcc
B_DAT3
B_DAT7
B_BWEb
Vcc
B_DATa0
B_DATa4
B_BWEa
Vcc
B_DATa1
B_DATa5
B_ZZ
B_DATa2
B_DATa6
B_ADR
Vcc
B_DATa3
B_DATa7
B_ADR
B_ADR
B_ADR1
B_ADR
B_ADR
B_DATd7
B_DATd3
Vss
NC
NC
M
N
P
R
T
U
V
W
B_ADR
B_ADR
B_ADR
B_ADR
B_ADR
NC
B_ADR
B_ADR
B_ADR0
B_ADR
B_ADR
NC
B_CKE#
B_GWE#
B_CS2#
B_CS1#
B_DATc5
B_DATc1
Vcc
B_CK
Vcc
Vcc
Vcc
Vcc
Vcc
Vss
Vcc
Vcc
Vcc
Vcc
Vcc
NC
B_CS2
B_DATc6
B_DATc2
B_BWEc
B_DATc7
B_DATc3
B_BWEd
B_DATd4
B_DATd0
B_LBO#
B_DATd5
B_DATd1
B_ADR
B_DATd6
B_DATd2
B_DATc4
B_DATc0
Vss
Vss
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April, 2002
Rev. 0
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com