Datasheet > 存储 > DRAM> W332M64V-125SBM

W332M64V-125SBM

更新时间： 2024-09-18 03:17:51

品牌	Logo	应用领域
WEDC		存储内存集成电路动态存储器
页数	文件大小	规格书
15页	304K
描述
32Mx64 Synchronous DRAM

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W332M64V-125SBM 数据手册

W332M64V-XSBX

White Electronic Designs

32Mx64 Synchronous DRAM

FEATURES

GENERAL DESCRIPTION

ꢀ High Frequency = 100, 125, 133MHz

ꢀ Package:

The 256MByte (2Gb) SDRAM is a high-speed CMOS,

dynamic random-access, memory using 4 chips containing

536,870,912 bits. Each chip is internally conﬁgured as a

quad-bank DRAM with a synchronous interface. Each of

the chip’s 134,217,728-bit banks is organized as 8,192

rows by 1,024 columns by 16 bits.

•

208 Plastic Ball Grid Array (PBGA), 13 x 22mm

ꢀ 3.3V 0.3V power supply

ꢀ Fully Synchronous; all signals registered on positive

edge of system clock cycle

Read and write accesses to the SDRAM are burst ori-

ented; accesses start at a selected location and continue

for a programmed number of locations in a programmed

sequence. Accesses begin with the registration of an

ACTIVE command, which is then followed by a READ or

WRITE command. The address bits registered coincident

with the ACTIVE command are used to select the bank

and row to be accessed (BA0, BA1 select the bank; A0-

12 select the row). The address bits registered coincident

with the READ or WRITE command are used to select the

starting column location for the burst access.

The SDRAM provides for programmable READ or WRITE

burst lengths of 1, 2, 4 or 8 locations, or the full page, with

a burst terminate option.AnAUTO PRECHARGE function

may be enabled to provide a self-timed row precharge that

is initiated at the end of the burst sequence.

ꢀ Internal pipelined operation; column address can be

changed every clock cycle

ꢀ Internal banks for hiding row access/precharge

ꢀ Programmable Burst length 1,2,4,8 or full page

ꢀ 8192 refresh cycles

ꢀ Commercial, Industrial and Military Temperature

Ranges

ꢀ Organized as 32M x 64

ꢀ Weight: W332M64V-XSBX - 1.4 grams typical

BENEFITS

ꢀ 73% SPACE SAVINGS

ꢀ Reduced part count

ꢀ Reduced trace lengths for lower parasitic

capacitance

ꢀ Suitable for hi-reliability applications

The 2Gb SDRAM uses an internal pipelined architecture to

achieve high-speed operation. This architecture is compatible

with the 2n rule of prefetch architectures, but it also allows

the column address to be changed on every clock cycle to

achieve a high-speed, fully random access. Precharging

one bank while accessing one of the other three banks

will hide the precharge cycles and provide seamless, high-

speed, random-access operation.

* This product is to change without notice.

The 2Gb SDRAM is designed to operate at 3.3V. An auto

refresh mode is provided, along with a power-saving,

power-down mode.

Discrete Approach

ACTUAL SIZE

11.9

TSOP

22.3

TSOP

hWtieElcoertniDceisngs

Area

4 x 265mm²= 1060mm²

286mm²

73%

September 2005

Rev. 3

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

12 3 4 5 6 7...15

中文翻译

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与W332M64V-125SBM相关器件

型号	品牌	获取价格	描述	数据表
W332M64V-133BC	WEDC	获取价格	32Mx64 Synchronous DRAM
W332M64V-133BI	WEDC	获取价格	32Mx64 Synchronous DRAM
W332M64V-133BM	WEDC	获取价格	32Mx64 Synchronous DRAM
W332M64V-133SBC	WEDC	获取价格	32Mx64 Synchronous DRAM
W332M64V-133SBI	WEDC	获取价格	32Mx64 Synchronous DRAM
W332M64V-133SBI	MICROSEMI	获取价格	Synchronous DRAM, 32MX64, 5.5ns, CMOS, PBGA208, 13 X 22 MM, PLASTIC, BGA-208
W332M64V-133SBM	WEDC	获取价格	32Mx64 Synchronous DRAM
W332M64V-XBX	WEDC	获取价格	32Mx64 Synchronous DRAM
W332M64V-XSBX	WEDC	获取价格	32Mx64 Synchronous DRAM
W332M72V-100BC	WEDC	获取价格	32Mx72 Synchronous DRAM

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