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W332M64V-133SBI PDF预览

W332M64V-133SBI

更新时间： 2024-09-18 20:12:47
品牌 Logo 应用领域
美高森美 - MICROSEMI 时钟动态存储器内存集成电路
页数 文件大小 规格书
14页 854K
描述
Synchronous DRAM, 32MX64, 5.5ns, CMOS, PBGA208, 13 X 22 MM, PLASTIC, BGA-208

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W332M64V-133SBI 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Transferred零件包装代码：BGA
包装说明：BGA,针数：208
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.36风险等级：5.4
访问模式：MULTI BANK PAGE BURST最长访问时间：5.5 ns
其他特性：AUTO/SELF REFRESH; LG-MAX; WD-MAX; SEATED HT-CALCULATEDJESD-30 代码：R-PBGA-B208
长度：22.15 mm内存密度：2147483648 bit
内存集成电路类型：SYNCHRONOUS DRAM内存宽度：64
功能数量：1端口数量：1
端子数量：208字数：33554432 words
字数代码：32000000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：32MX64封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装形状：RECTANGULAR
封装形式：GRID ARRAY峰值回流温度（摄氏度）：225
认证状态：Not Qualified座面最大高度：2.77 mm
自我刷新：YES最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：30宽度：13.15 mm
Base Number Matches：1

W332M64V-133SBI 数据手册

 浏览型号W332M64V-133SBI的Datasheet PDF文件第2页浏览型号W332M64V-133SBI的Datasheet PDF文件第3页浏览型号W332M64V-133SBI的Datasheet PDF文件第4页浏览型号W332M64V-133SBI的Datasheet PDF文件第5页浏览型号W332M64V-133SBI的Datasheet PDF文件第6页浏览型号W332M64V-133SBI的Datasheet PDF文件第7页 
W332M64V-XSBX  
32Mx64 Synchronous DRAM  
FEATURES  
GENERAL DESCRIPTION  
 High Frequency = 100, 125, 133MHz  
The 256MByte (2Gb) SDRAM is a high-speed CMOS, dynamic  
random-access, memory using 4 chips containing 536,870,912  
bits. Each chip is internally configured as a quad-bank DRAM with  
a synchronous interface. Each of the chip’s 134,217,728-bit banks  
is organized as 8,192 rows by 1,024 columns by 16 bits.  
 Package:  
• 208 Plastic Ball Grid Array (PBGA), 13 x 22mm  
 3.3V ±0.3V power supply  
 Fully Synchronous; all signals registered on positive edge  
Read and write accesses to the SDRAM are burst oriented;  
accesses start at a selected location and continue for a  
programmed number of locations in a programmed sequence.  
Accesses begin with the registration of an ACTIVE command,  
which is then followed by a READ or WRITE command. The  
address bits registered coincident with the ACTIVE command  
are used to select the bank and row to be accessed (BA0, BA1  
select the bank;A0-12 select the row). The address bits registered  
coincident with the READ or WRITE command are used to select  
the starting column location for the burst access.  
of system clock cycle  
 Internal pipelined operation; column address can be  
changed every clock cycle  
 Internal banks for hiding row access/precharge  
 Programmable Burst length 1,2,4,8 or full page  
 8192 refresh cycles  
 Commercial, Industrial and Military Temperature Ranges  
 Organized as 32M x 64  
The SDRAM provides for programmable READ or WRITE burst  
lengths of 1, 2, 4 or 8 locations, or the full page, with a burst  
terminate option.AnAUTO PRECHARGE function may be enabled  
to provide a self-timed row precharge that is initiated at the end  
of the burst sequence.  
 Weight: W332M64V-XSBX - 1.4 grams typical  
BENEFITS  
 73% SPACE SAVINGS  
The 2Gb SDRAM uses an internal pipelined architecture to achieve  
high-speed operation. This architecture is compatible with the 2n rule  
of prefetch architectures, but it also allows the column address to  
be changed on every clock cycle to achieve a high-speed, fully  
random access. Precharging one bank while accessing one of  
the other three banks will hide the precharge cycles and provide  
seamless, high-speed, random-access operation.  
 Reduced part count  
 Reduced trace lengths for lower parasitic capacitance  
 Suitable for hi-reliability applications  
* This product is to change without notice.  
The 2Gb SDRAM is designed to operate at 3.3V. An auto refresh  
mode is provided, along with a power-saving, power-down mode.  
All inputs and outputs are LVTTL compatible. SDRAMs offer  
substantial advances in DRAM operating performance, including  
the ability to synchronously burst data at a high data rate with  
automatic column-address generation, the ability to interleave  
between internal banks in order to hide precharge time and the  
capability to randomly change column addresses on each clock  
cycle during a burst access.  
Continued on page 4  
DENSITY COMPARISONS  
Discrete Approach (mm)  
W332M64V-XSBX  
S
11.9  
11.9  
11.9  
11.9  
A
V
I
N
G
S
22  
54  
TSOP  
54  
TSOP  
54  
TSOP  
54  
TSOP  
22.3  
13  
Area  
4 x 265mm2 = 1,060mm2  
286mm2  
73%  
Microsemi Corporation reserves the right to change products or specifications without notice.  
December 2011 © 2011 Microsemi Corporation. All rights reserved.  
Rev. 6  
1
Microsemi Corporation • (602) 437-1520 • www.whiteedc.com  
www.microsemi.com/pmgp  
1234567...14

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W332M64V-XSBX WEDC

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W332M72V-100BI WEDC

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 		32Mx72 Synchronous DRAM
W332M72V-100BM WEDC

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 		32Mx72 Synchronous DRAM
W332M72V-100SBC MICROSEMI

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W332M72V-100SBC WEDC

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 		32Mx72 Synchronous DRAM
W332M72V-100SBI WEDC

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 		32Mx72 Synchronous DRAM
W332M72V-100SBI MICROSEMI

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 		Synchronous DRAM, 32MX72, 7ns, CMOS, PBGA208, 16 X 22 MM, PLASTIC, BGA-208

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