Datasheet > W332M72V-133SBM

W332M72V-133SBM

更新时间： 2024-11-25 20:19:03

品牌	Logo	应用领域
美高森美 - MICROSEMI		动态存储器内存集成电路
页数	文件大小	规格书
15页	257K
描述
Synchronous DRAM, 32MX72, 5.5ns, CMOS, PBGA208, 16 X 22 MM, PLASTIC, BGA-208

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W332M72V-133SBM 数据手册

W332M72V-XBX

White Electronic Designs

32Mx72 Synchronous DRAM

FEATURES

GENERAL DESCRIPTION

ꢀ

High Frequency = 100, 125, 133MHz

Package:

The 256MByte (2Gb) SDRAM is a high-speed CMOS,

dynamic random-access, memory using 5 chips containing

536,870,912 bits. Each chip is internally conﬁgured as a

quad-bank DRAM with a synchronous interface. Each of

the chip’s 134,217,728-bit banks is organized as 8,192

rows by 1,024 columns by 16 bits.

• 219 Plastic Ball Grid Array (PBGA), 32 x 25mm

3.3V 0.3V power supply

Fully Synchronous; all signals registered on positive

edge of system clock cycle

ꢀ

Read and write accesses to the SDRAM are burst ori-

ented; accesses start at a selected location and continue

for a programmed number of locations in a programmed

sequence. Accesses begin with the registration of an

ACTIVE command, which is then followed by a READ or

WRITE command. The address bits registered coincident

with the ACTIVE command are used to select the bank

and row to be accessed (BA0, BA1 select the bank; A0-

12 select the row). The address bits registered coincident

with the READ or WRITE command are used to select the

starting column location for the burst access.

ꢀ

Internal pipelined operation; column address can be

changed every clock cycle

ꢀ

Internal banks for hiding row access/precharge

Programmable Burst length 1,2,4,8 or full page

8,192 refresh cycles

Commercial, Industrial and Military Temperature

Ranges

ꢀ

Organized as 32M x 72

Weight: W332M72V-XBX – 3.5 grams typical

The SDRAM provides for programmable READ or WRITE

burst lengths of 1, 2, 4 or 8 locations, or the full page, with

a burst terminate option.AnAUTO PRECHARGE function

may be enabled to provide a self-timed row precharge that

is initiated at the end of the burst sequence.

BENEFITS

ꢀ

40% SPACE SAVINGS

Reduced part count

Reduced I/O count

• 19% I/O Reduction

The 2Gb SDRAM uses an internal pipelined architecture to

achieve high-speed operation. This architecture is compatible

with the 2n rule of prefetch architectures, but it also allows

the column address to be changed on every clock cycle to

achieve a high-speed, fully random access. Precharging

one bank while accessing one of the other three banks

will hide the precharge cycles and provide seamless, high-

speed, random-access operation.

ꢀ

Reduced trace lengths for lower parasitic

capacitance

ꢀ Suitable for hi-reliability applications

ꢀ

Laminate interposer for optimum TCE match

ꢀ

Pinout compatible with lower desities

WEDPN4M72V-XB2X, WEDPN8M72V-XB2X and

WEDPN16M72V-XB2X

The 2Gb SDRAM is designed to operate at 3.3V. An auto

refresh mode is provided, along with a power-saving,

power-down mode.

* This product is subject to change without notice.

Discrete Approach

11.9

ACTUAL SIZE

11.9

TSOP

White Electronic Designs

22.3

W332M72V-XBX

Area

5 x 265mm²= 1328mm²

5 x 54 pins = 270 pins

800mm²

219 Balls

40%

19%

I/O

Count

March 2006

Rev. 3

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

12 3 4 5 6 7...15

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与W332M72V-133SBM相关器件

型号	品牌	获取价格	描述	数据表
W332M72V-XBX	WEDC	获取价格	32Mx72 Synchronous DRAM
W332M72V-XSBX	WEDC	获取价格	32Mx72 Synchronous DRAM
W3334B0100	PULSE	获取价格	FPC ANTENNA 2.4
W3334B0127	PULSE	获取价格	FPC ANTENNA 2.4
W3334B0150	PULSE	获取价格	FPC ANTENNA 2.4
W3334B0250	PULSE	获取价格	FPC ANTENNA 2.4
W3334B0290	PULSE	获取价格	FPC ANTENNA 2.4
W3334BD0150	PULSE	获取价格	FPC Antenna 2.4/5.xGHz/DSRC
W3334XXXXX	PULSE	获取价格	FPC Antenna 2.4/5.xGHz/DSRC
W33D0001	ETC	获取价格

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