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V62/04668-01XE

更新时间： 2024-02-15 07:48:37
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德州仪器 - TI 触发器输出元件
页数 文件大小 规格书
9页 412K
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OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

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V62/04668-01XE 数据手册

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SN74LVC574A-EP  
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCAS750A–DECEMBER 2003–REVISED AUGUST 2005  
FEATURES  
•
Controlled Baseline  
•
•
Supports Mixed-Mode Signal Operation on All  
Ports (5-V Input/Output Voltage With 3.3-V  
– One Assembly/Test Site, One Fabrication  
Site  
VCC  
)
Ioff Supports Partial-Power-Down Mode  
Operation  
•
•
Extended Temperature Performance of –40°C  
to 125°C  
Enhanced Diminishing Manufacturing  
Sources (DMS) Support  
DW OR PW PACKAGE  
(TOP VIEW)  
•
•
•
•
•
•
Enhanced Product-Change Notification  
(1)  
OE  
1D  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
Qualification Pedigree  
1Q  
Operates From 2 V to 3.6 V  
Inputs Accept Voltages to 5.5 V  
Max tpd of 7 ns at 3.3 V  
2D  
3D  
4D  
5D  
18 2Q  
17 3Q  
16  
15  
14  
13  
12  
11  
4Q  
5Q  
6Q  
7Q  
8Q  
CLK  
Typical VOLP (Output Ground Bounce) <0.8 V  
at VCC = 3.3 V, TA = 25°C  
6D  
•
Typical VOHV (Output VOH Undershoot) >2 V at  
VCC = 3.3 V, TA = 25°C  
7D  
8D  
GND  
(1) Component qualification in accordance with JEDEC and  
industry standards to ensure reliable operation over an  
extended temperature range. This includes, but is not limited  
to, Highly Accelerated Stress Test (HAST) or biased 85/85,  
temperature cycle, autoclave or unbiased HAST,  
electromigration, bond intermetallic life, and mold compound  
life. Such qualification testing should not be viewed as  
justifying use of this component beyond specified  
performance and environmental limits.  
DESCRIPTION/ORDERING INFORMATION  
The SN74LVC574A-EP octal edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCC operation.  
This device features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance  
loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working  
registers.  
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels at the data (D) inputs.  
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or  
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the  
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines  
without interface or pullup components.  
OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
Reel of 2000  
Reel of 2000  
ORDERABLE PART NUMBER  
SN74LVC574AQDWREP  
TOP-SIDE MARKING  
C574AEP  
C574AEP  
SOIC – DW  
–40°C to 125°C  
TSSOP – PW  
SN74LVC574AQPWREP  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2003–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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