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V62/04677-01XE PDF预览

V62/04677-01XE

更新时间: 2024-11-18 11:58:15
品牌 Logo 应用领域
德州仪器 - TI 输出元件
页数 文件大小 规格书
10页 300K
描述
3.3-V ABT OCTAL REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS

V62/04677-01XE 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP, TSSOP24,.25针数:24
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:16 weeks风险等级:5.46
控制类型:INDEPENDENT CONTROL计数方向:BIDIRECTIONAL
系列:LVTJESD-30 代码:R-PDSO-G24
JESD-609代码:e4长度:7.8 mm
负载电容(CL):15 pF逻辑集成电路类型:REGISTERED BUS TRANSCEIVER
最大I(ol):0.064 A湿度敏感等级:1
位数:8功能数量:1
端口数量:2端子数量:24
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP24,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TR
峰值回流温度(摄氏度):260电源:3.3 V
最大电源电流(ICC):0.005 mAProp。Delay @ Nom-Sup:3.7 ns
传播延迟(tpd):5.9 ns认证状态:Not Qualified
施密特触发器:No座面最大高度:1.2 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
翻译:N/A宽度:4.4 mm

V62/04677-01XE 数据手册

 浏览型号V62/04677-01XE的Datasheet PDF文件第2页浏览型号V62/04677-01XE的Datasheet PDF文件第3页浏览型号V62/04677-01XE的Datasheet PDF文件第4页浏览型号V62/04677-01XE的Datasheet PDF文件第5页浏览型号V62/04677-01XE的Datasheet PDF文件第6页浏览型号V62/04677-01XE的Datasheet PDF文件第7页 
ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢃ ꢉꢊ ꢋꢌ  
ꢉ ꢍꢉ ꢊꢅ ꢎꢏꢆ ꢐ ꢑꢆꢎꢄ ꢒꢋꢓ ꢔ ꢀꢆ ꢋꢒꢋꢕ ꢆ ꢒꢎꢁꢀ ꢑꢋ ꢔ ꢅꢋ ꢒ  
ꢖ ꢔꢆ ꢇ ꢉ ꢊꢀꢆꢎꢆ ꢋ ꢐ ꢗꢆ ꢌꢗ ꢆꢀ  
SCBS772 − NOVEMBER 2003  
D
D
D
D
D
Controlled Baseline  
− One Assembly/Test Site, One Fabrication  
Site  
D
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
Enhanced Diminishing Manufacturing  
Sources (DMS) Support  
D
D
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
Enhanced Product-Change Notification  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
Qualification Pedigree  
Supports Mixed-Mode Signal Operation  
(5-V Input and Output Voltages With  
PW PACKAGE  
(TOP VIEW)  
3.3-V V  
)
CC  
D
D
D
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
LEBA  
OEBA  
A1  
V
CC  
CEBA  
= 3.3 V, T = 25°C  
A
2
Supports Unregulated Battery Operation  
Down to 2.7 V  
3
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
4
A2  
A3  
A4  
A5  
A6  
A7  
A8  
I
and Power-Up 3-State Support Hot  
off  
5
Insertion  
6
Component qualification in accordance with JEDEC and industry  
standards to ensure reliable operation over an extended  
temperature range. This includes, but is not limited to, Highly  
Accelerated Stress Test (HAST) or biased 85/85, temperature  
cycle, autoclave or unbiased HAST, electromigration, bond  
intermetallic life, and mold compound life. Such qualification  
testing should not be viewed as justifying use of this component  
beyond specified performance and environmental limits.  
7
8
9
10  
11  
12  
CEAB  
GND  
LEAB  
OEAB  
description/ordering information  
This octal transceiver is designed specifically for low-voltage (3.3-V) V  
provide a TTL interface to a 5-V system environment.  
operation, but with the capability to  
CC  
The SN74LVTH543 contains two sets of D-type latches for temporary storage of data flowing in either direction.  
Separate latch-enable (LEAB or LEBA) and output-enable (OEAB or OEBA) inputs are provided for each  
register, to permit independent control in either direction of data flow.  
The A-to-B enable (CEAB) input must be low to enter data from A or to output data from B. If CEAB is low and  
LEAB is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts the A latches  
in the storage mode. With CEAB and OEAB both low, the 3-state B outputs are active and reflect the data present  
at the output of the A latches. Data flow from B to A is similar, but requires using the CEBA, LEBA, and OEBA  
inputs.  
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors  
with the bus-hold circuitry is not recommended.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
T
A
PACKAGE  
−40°C to 85°C  
TSSOP − PW Tape and reel  
SN74LVTH543IPWREP  
LH543EP  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢆꢣ  
Copyright 2003, Texas Instruments Incorporated  
ꢟ ꢣ ꢠ ꢟꢘ ꢙꢬ ꢛꢚ ꢞ ꢦꢦ ꢤꢞ ꢜ ꢞ ꢝ ꢣ ꢟ ꢣ ꢜ ꢠ ꢍ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

V62/04677-01XE 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVTH543IPWREP TI

完全替代

3.3-V ABT OCTAL REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS
SN74LVTH543PWR TI

完全替代

3.3 V ABT OCTAL REGISTERED TRANSCEIVERS WITH 3 STATE OUTPUTS
SN74LVTH543PW TI

完全替代

3.3-V ABT OCTAL REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

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