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V62/04689-01XE PDF预览

V62/04689-01XE

更新时间： 2024-09-30 12:21:51
品牌 Logo 应用领域
德州仪器 - TI 移位寄存器触发器逻辑集成电路光电二极管
页数 文件大小 规格书
16页 632K
描述
8-BIT PARALLEL-LOAD SHIFT REGISTER

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V62/04689-01XE 技术参数

是否无铅： 含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：GREEN, PLASTIC, SOIC-16针数：16
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.16Is Samacsys：N
其他特性：CLOCK INHIBIT计数方向：RIGHT
系列：HC/UHJESD-30 代码：R-PDSO-G16
JESD-609代码：e4长度：9.9 mm
逻辑集成电路类型：PARALLEL IN SERIAL OUT最大频率@ Nom-Sup：25000000 Hz
湿度敏感等级：1位数：8
功能数量：1端子数量：16
最高工作温度：125 °C最低工作温度：-40 °C
输出极性：COMPLEMENTARY封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP16,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260电源：2/6 V
传播延迟（tpd）：225 ns认证状态：Not Qualified
座面最大高度：1.75 mm子类别：Shift Registers
最大供电电压 (Vsup)：6 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：AUTOMOTIVE
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：3.9 mm最小 fmax：25 MHz
Base Number Matches：1

V62/04689-01XE 数据手册

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SCLS473A − APRIL 2003 − REVISED JANUARY 2004  
D
Controlled Baseline  
− One Assembly/Test Site, One Fabrication  
Site  
D
D
D
D
D
D
4-mA Output Drive at 5 V  
Low Input Current of 1 µA Max  
Complementary Outputs  
D
D
Extended Temperature Performance of Up  
To −55°C to 125°C  
Enhanced Diminishing Manufacturing  
Sources (DMS) Support  
Direct Overriding Load (Data) Inputs  
Gated Clock Inputs  
Parallel-to-Serial Data Conversion  
D
D
D
D
D
D
Enhanced Product-Change Notification  
D OR PW PACKAGE  
(TOP VIEW)  
†
Qualification Pedigree  
2-V to 6-V V  
Operation  
CC  
SH/LD  
CLK  
E
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
V
CC  
CLK INH  
Outputs Can Drive Up To 10 LSTTL Loads  
Low Power Consumption, 80-µA Max I  
CC  
D
C
B
A
Typical t = 13 ns  
pd  
F
G
H
†
Component qualification in accordance with JEDEC and industry  
standards to ensure reliable operation over an extended  
temperature range. This includes, but is not limited to, Highly  
Accelerated Stress Test (HAST) or biased 85/85, temperature  
cycle, autoclave or unbiased HAST, electromigration, bond  
intermetallic life, and mold compound life. Such qualification  
testing should not be viewed as justifying use of this component  
beyond specified performance and environmental limits.  
Q
SER  
H
GND  
Q
H
description/ordering information  
The SN74HC165 is an 8-bit parallel-load shift register that, when clocked, shifts the data toward a serial (Q )  
H
output. Parallel-in access to each stage is provided by eight individual direct data (A−H) inputs that are enabled  
by a low level at the shift/load (SH/LD) input. The SN74HC165 device also features a clock-inhibit (CLK INH)  
function and a complementary serial (Q ) output.  
H
Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and CLK  
INH is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a low-to-high  
transition of CLK INH also accomplish clocking, CLK INH should be changed to the high level only while CLK  
is high. Parallel loading is inhibited when SH/LD is held high. While SH/LD is low, the parallel inputs to the  
register are enabled independently of the levels of the CLK, CLK INH, or serial (SER) inputs.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
‡
PACKAGE  
T
A
SOIC − D  
Tape and reel  
Tape and reel  
Tape and reel  
SN74HC165QDREP  
SN74HC165QPWREP  
SN74HC165MDREP  
HC165EP  
−40°C to 125°C  
−55°C to 125°C  
TSSOP − PW  
SOIC − D  
HC165EP  
HC165MEP  
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
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Copyright 2004, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...16

中文翻译

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