ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢃ ꢉꢊ ꢋꢌ
ꢍ ꢎꢍ ꢊꢅ ꢏꢐꢆ ꢑ ꢒꢆꢏꢄ ꢐꢓꢔ ꢔ ꢋꢕ ꢖꢗ ꢕ ꢘꢅ ꢋ ꢕ
ꢙ ꢘꢆ ꢇ ꢍ ꢊꢀꢆꢏꢆ ꢋ ꢑ ꢓꢆ ꢌꢓ ꢆꢀ
SCBS766 − NOVEMBER 2003
D
D
D
D
D
Controlled Baseline
− One Assembly/Test Site, One Fabrication
Site
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Enhanced Diminishing Manufacturing
Sources (DMS) Support
D
D
Latch-Up Performance Exceeds 500 mA Per
JESD 17
Enhanced Product-Change Notification
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
†
Qualification Pedigree
Supports Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
PW PACKAGE
(TOP VIEW)
3.3-V V
)
CC
D
D
D
Supports Unregulated Battery Operation
Down to 2.7 V
1OE
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
V
CC
19 2OE
18 1Y1
1
2
3
4
5
6
7
8
9
10
20
Typical V
<0.8 V at V
(Output Ground Bounce)
OLP
CC
= 3.3 V, T = 25°C
A
17
16
15
14
13
12
11
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
I
and Power-Up 3-State Support Hot
off
Insertion
†
Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
description/ordering information
This octal buffer and line driver is designed specifically for low-voltage (3.3-V) V
capability to provide a TTL interface to a 5-V system environment.
operation, but with the
CC
This device is organized as two 4-bit buffer/line drivers with separate output-enable (OE) inputs. When OE is
low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the
high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup
CC
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
This device is fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry
off
off
disables the outputs, preventing damaging current backflow through the device when it is powered down. The
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
‡
T
PACKAGE
TSSOP − PW
A
−40°C to 85°C
Tape and reel SN74LVTH240IPWREP LH240EP
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
ꢌ
ꢌ
ꢕ
ꢑ
ꢩ
ꢗ
ꢤ
ꢓ
ꢒ
ꢢ
ꢆ
ꢣ
ꢘ
ꢝ
ꢑ
ꢛ
ꢁ
ꢜ
ꢗ
ꢏ
ꢆ
ꢏ
ꢚ
ꢛ
ꢥ
ꢜ
ꢝ
ꢣ
ꢞ
ꢟ
ꢠ
ꢠ
ꢡ
ꢡ
ꢚ
ꢚ
ꢝ
ꢝ
ꢛ
ꢛ
ꢚ
ꢢ
ꢢ
ꢦ
ꢣ
ꢤ
ꢞ
ꢞ
ꢥ
ꢥ
ꢛ
ꢡ
ꢠ
ꢟ
ꢢ
ꢢ
ꢝ
ꢜ
ꢦ
ꢆꢥ
ꢤ
ꢧ
ꢢ
ꢨ
ꢚ
ꢣ
ꢠ
ꢢ
ꢡ
ꢚ
ꢡ
ꢝ
ꢞ
ꢛ
ꢤ
ꢩ
ꢠ
ꢛ
ꢡ
ꢡ
ꢥ
ꢢ
ꢎ
Copyright 2003, Texas Instruments Incorporated
ꢞ
ꢝ
ꢣ
ꢡ
ꢝ
ꢞ
ꢟ
ꢡ
ꢝ
ꢢ
ꢦ
ꢚ
ꢜ
ꢚ
ꢣ
ꢥ
ꢞ
ꢡ
ꢪ
ꢡ
ꢥ
ꢞ
ꢝ
ꢜ
ꢫ
ꢠ
ꢘ
ꢛ
ꢟ
ꢥ
ꢢ
ꢡ
ꢠ
ꢛ
ꢩ
ꢠ
ꢞ
ꢩ
ꢬ
ꢠ
ꢡ ꢥ ꢢ ꢡꢚ ꢛꢮ ꢝꢜ ꢠ ꢨꢨ ꢦꢠ ꢞ ꢠ ꢟ ꢥ ꢡ ꢥ ꢞ ꢢ ꢎ
ꢞ
ꢞ
ꢠ
ꢛ
ꢡ
ꢭ
ꢎ
ꢌ
ꢞ
ꢝ
ꢩ
ꢤ
ꢣ
ꢡ
ꢚ
ꢝ
ꢛ
ꢦ
ꢞ
ꢝ
ꢣ
ꢥ
ꢢ
ꢢ
ꢚ
ꢛ
ꢮ
ꢩ
ꢝ
ꢥ
ꢢ
ꢛ
ꢝ
ꢡ
ꢛ
ꢥ
ꢣ
ꢥ
ꢢ
ꢢ
ꢠ
ꢞ
ꢚ
ꢨ
ꢭ
ꢚ
ꢛ
ꢣ
ꢨ
ꢤ
ꢩ
ꢥ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265