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UPA2710GR PDF预览

UPA2710GR

更新时间: 2024-10-29 22:38:43
品牌 Logo 应用领域
日电电子 - NEC 晶体晶体管功率场效应晶体管开关脉冲光电二极管
页数 文件大小 规格书
7页 77K
描述
SWITCHING P-CHANNEL POWER MOSFET

UPA2710GR 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:POWER, SOP-8Reach Compliance Code:compliant
风险等级:5.84Is Samacsys:N
雪崩能效等级(Eas):22.5 mJ配置:SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压:30 V最大漏极电流 (ID):15 A
最大漏源导通电阻:0.011 ΩFET 技术:METAL-OXIDE SEMICONDUCTOR
JESD-30 代码:R-PDSO-G6JESD-609代码:e0
元件数量:1端子数量:6
工作模式:ENHANCEMENT MODE封装主体材料:PLASTIC/EPOXY
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED极性/信道类型:P-CHANNEL
最大脉冲漏极电流 (IDM):100 A认证状态:Not Qualified
表面贴装:YES端子面层:TIN LEAD
端子形式:GULL WING端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED晶体管应用:SWITCHING
晶体管元件材料:SILICONBase Number Matches:1

UPA2710GR 数据手册

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DATA SHEET  
MOS FIELD EFFECT TRANSISTOR  
µPA2710GR  
SWITCHING  
P-CHANNEL POWER MOS FET  
DESCRIPTION  
PACKAGE DRAWING (Unit: mm)  
The µPA2710GR is P-Channel MOS Field Effect Transistor  
designed for power management applications of notebook  
computers and Li-ion battery protection circuit.  
8
5
1, 2, 3  
4
: Source  
: Gate  
5, 6, 7, 8 : Drain  
FEATURES  
Low on-state resistance  
RDS(on)1 = 5.5 mMAX. (VGS = –10 V, ID = –7.5 A)  
RDS(on)2 = 9.0 mMAX. (VGS = –4.5 V, ID = –7.5 A)  
RDS(on)3 = 11 mMAX. (VGS = –4.0 V, ID = –7.5 A)  
Low Ciss: Ciss = 4300 pF TYP.  
6.0 ±0.3  
4.4  
1
4
5.37 MAX.  
0.8  
Small and surface mount package (Power SOP8)  
0.5 ±0.2  
0.10  
1.27 0.78 MAX.  
ORDERING INFORMATION  
+0.10  
0.40  
0.12 M  
–0.05  
PART NUMBER  
PACKAGE  
µPA2710GR  
Power SOP8  
ABSOLUTE MAXIMUM RATINGS (TA = 25°C, All terminals are connected.)  
Drain to Source Voltage (VGS = 0 V)  
Gate to Source Voltage (VDS = 0 V)  
Drain Current (DC)  
VDSS  
VGSS  
ID(DC)  
ID(pulse)  
PT1  
–30  
V
m20  
V
EQUIVALENT CIRCUIT  
m15  
A
Drain  
Drain Current (pulse) Note1  
m100  
A
Note2  
Total Power Dissipation  
2
W
W
°C  
°C  
A
Body  
Note3  
Total Power Dissipation  
PT2  
2
150  
Diode  
Gate  
Channel Temperature  
Tch  
Storage Temperature  
Tstg  
–55 to + 150  
15  
Single Avalanche Current Note4  
Single Avalanche Energy Note4  
Notes 1. PW 10 µs, Duty Cycle 1%  
Source  
IAS  
EAS  
22.5  
mJ  
2. Mounted on ceramic substrate of 1200 mm2 x 2.2 mm  
3. Mounted on a glass epoxy board (1 inch x 1 inch x 0.8 mm), PW = 10 sec  
4. Starting Tch = 25°C, VDD = –15 V, RG = 25 , L = 100 µH, VGS = –20 0 V  
Remark Strong electric field, when exposed to this device, can cause destruction of the gate oxide and ultimately  
degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible,  
and quickly dissipate it once, when it has occurred.  
The information in this document is subject to change without notice. Before using this document, please  
confirm that this is the latest version.  
Not all products and/or types are available in every country. Please check with an NEC Electronics  
sales representative for availability and additional information.  
The mark shows major revised points.  
Document No. G15978EJ3V0DS00 (3rd edition)  
Date Published February 2003 NS CP(K)  
Printed in Japan  
2002  

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