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UL635H256S2C45 PDF预览

UL635H256S2C45

更新时间： 2024-09-20 20:13:19
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
14页 187K
描述
32KX8 NON-VOLATILE SRAM, 45ns, PDSO28, 0.330 INCH, SOP2-28

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中文翻译

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UL635H256S2C45 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：SOIC包装说明：SOP,
针数：28Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.32.00.41
风险等级：5.82最长访问时间：45 ns
JESD-30 代码：R-PDSO-G28JESD-609代码：e0
内存密度：262144 bit内存集成电路类型：NON-VOLATILE SRAM
内存宽度：8功能数量：1
端子数量：28字数：32768 words
字数代码：32000工作模式：ASYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：32KX8封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE并行/串行：PARALLEL
认证状态：Not Qualified最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn85Pb15)
端子形式：GULL WING端子位置：DUAL
Base Number Matches：1

UL635H256S2C45 数据手册

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Obsolete - Not Recommended for New Designs  
UL635H256  
Low Voltage PowerStore 32K x 8 nvSRAM  
Features  
Description  
• High-performance CMOS non-  
The UL635H256 has two separate The UL635H256 combines the  
volatile static RAM 32768 x 8 bits modes of operation: SRAM mode high performance and ease of use  
• 35 and 45 ns Access Times  
• 15 and 20 ns Output Enable  
Access Times  
and nonvolatile mode. In SRAM of a fast SRAM with nonvolatile  
mode, the memory operates as an data integrity.  
ordinary static RAM. In nonvolatile STORE cycles also may be initia-  
operation, data is transferred in ted under user control via a soft-  
parallel from SRAM to EEPROM or ware sequence.  
• ICC = 8 mA typ. at 200 ns Cycle  
Time  
• Automatic STORE to EEPROM  
on Power Down using system  
capacitance  
from EEPROM to SRAM. In this Once a STORE cycle is initiated,  
mode SRAM functions are disab- further input or output are disabled  
led.  
until the cycle is completed.  
• Software initiated STORE  
• Automatic STORE Timing  
• 106 STORE cycles to EEPROM  
• 100 years data retention in  
EEPROM  
The UL635H256 is a fast static Because a sequence of addresses  
RAM (35 and 45 ns), with a nonvo- is used for STORE initiation, it is  
latile electrically erasable PROM important that no other read or  
(EEPROM) element incorporated write accesses intervene in the  
in each static memory cell. The sequence or the sequence will be  
• Automatic RECALL on Power Up SRAM can be read and written an  
aborted.  
• Software RECALL Initiation  
• Unlimited RECALL cycles from  
EEPROM  
unlimited number of times, while  
independent nonvolatile data resi-  
des in EEPROM. Data transfers  
from the SRAM to the EEPROM  
(the STORE operation) take place  
automatically upon power down  
using charge stored in system  
capacitance. Transfers from the  
EEPROM to the SRAM (the  
RECALL operation) take place  
automatically on powerup.  
RECALL cycles may also be initia-  
ted by a software sequence.  
Internally, RECALL is a two step  
procedure. First, the SRAM data is  
cleared and second, the nonvola-  
tile information is transferred into  
the SRAM cells.  
The RECALL operation in no way  
alters the data in the EEPROM  
cells. The nonvolatile data can be  
recalled an unlimited number of  
times.  
• Wide voltage range: 2.7 ... 3.6 V  
(3.0 ... 3.6 V for 35 ns type)  
• Operating temperature range:  
0 to 70 °C  
-40 to 85 °C  
• QS 9000 Quality Standard  
• ESD protection > 2000 V  
(MIL STD 883C M3015.7-HBM)  
• RoHS compliance and Pb- free  
• Package:SOP28 (330 mil)  
Pin Description  
Pin Configuration  
G
A11  
A9  
A8  
A13  
W
1
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
n.c.  
A10  
E
VCC  
W
A13  
A8  
A9  
A11  
G
A14  
A12  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
1
2
3
4
5
6
7
8
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
2
Signal Name Signal Description  
3
4
DQ7  
DQ6  
DQ5  
DQ4  
DQ3  
VSS  
DQ2  
DQ1  
DQ0  
A0  
A0 - A14  
Address Inputs  
Data In/Out  
5
6
DQ0 - DQ7  
n. c.  
VCC  
n. c.  
A14  
A12  
A7  
7
8
SOP  
TSOP  
Chip Enable  
E
A10  
E
9
10  
11  
12  
13  
14  
15  
16  
9
Output Enable  
Write Enable  
Power Supply Voltage  
Ground  
G
DQ7  
DQ6  
DQ5  
DQ4  
DQ3  
A0  
10  
11  
12  
13  
14  
DQ0  
DQ1  
DQ2  
VSS  
W
A6  
A5  
A1  
VCC  
VSS  
A4  
A2  
A3  
n.c.  
Top View  
Top View  
March 31, 2006  
STK Control #ML0059  
1
Rev 1.0  
1234567...14

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UL635H256S2K45G1 SIMTEK

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 		Low Voltage PowerStore 32K x 8 nvSRAM
UL635H256SC35 SIMTEK

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UL635H256SC35G1 SIMTEK

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UL635H256SC45 SIMTEK

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 		Low Voltage PowerStore 32K x 8 nvSRAM
UL635H256SC45G1 SIMTEK

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