UL635H256
Low Voltage PowerStore 32K x 8 nvSRAM
Features
Description
F High-performance CMOS non-
The UL635H256 has two separate high performance and ease of use
volatile static RAM 32768 x 8 bits modes of operation: SRAM mode of a fast SRAM with nonvolatile
F 45 and 55 ns Access Times
F 20 and 25 ns Output Enable
Access Times
F ICC = 8 mA at 200 ns Cycle Time
F Automatic STORE to EEPROM
on Power Down using system
capacitance
and nonvolatile mode. In SRAM data integrity.
mode, the memory operates as an STORE cycles also may be initia-
ordinary static RAM. In nonvolatile ted under user control via a soft-
operation, data is transferred in ware sequence.
parallel from SRAM to EEPROM or Once a STORE cycle is initiated,
from EEPROM to SRAM. In this further input or output are disabled
mode SRAM functions are disab- until the cycle is completed.
F Software initiated STORE
F Automatic STORE Timing
F 105 STORE cycles to EEPROM
F 10 years data retention in
EEPROM
led.
Because a sequence of addresses
The UL635H256 is a fast static is used for STORE initiation, it is
RAM (45 and 55 ns), with a nonvo- important that no other read or
latile electrically erasable PROM write accesses intervene in the
(EEPROM) element incorporated sequence or the sequence will be
F Automatic RECALL on Power Up in each static memory cell. The aborted.
F Software RECALL Initiation
F Unlimited RECALL cycles from
EEPROM
F Wide voltage range: 2.7 ... 3.6 V
F Operating temperature range:
0 to 70 °C
SRAM can be read and written an RECALL cycles may also be initia-
unlimited number of times, while ted by a software sequence.
independent nonvolatile data resi- Internally, RECALL is a two step
des in EEPROM. Data transfers procedure. First, the SRAM data is
from the SRAM to the EEPROM cleared and second, the nonvola-
(the STORE operation) take place tile information is transferred into
automatically upon power down the SRAM cells.
-40 to 85 °C
F CECC 90000 Quality Standard
F ESD protection > 2000 V
(MIL STD 883C M3015.7-HBM)
F Packages: SOP28 (330 mil)
TSOP32 (Type I)
using charge stored in system The RECALL operation in no way
capacitance. Transfers from the alters the data in the EEPROM
EEPROM to the SRAM (the cells. The nonvolatile data can be
RECALL operation) take place recalled an unlimited number of
automatically on powerup.
times.
The UL635H256 combines the
Pin Description
Pin Configuration
G
1
28
27
26
25
24
23
22
21
20
19
18
17
n.c.
A10
E
VCC
W
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
A14
A12
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
25
24
23
22
21
20
19
18
17
16
15
Signal Name Signal Description
A11
A9
2
3
A0 - A14
Address Inputs
Data In/Out
A8
4
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A13
W
5
DQ0 - DQ7
6
n. c.
VCC
n. c.
A14
A12
A7
7
Chip Enable
E
8
9
Output Enable
Write Enable
Power Supply Voltage
Ground
SOP
TSOP
G
10
11
12
13
14
15
16
32
31
30
29
9
A0
10
11
12
13
14
28
27
26
W
DQ0
DQ1
DQ2
VSS
A6
VCC
VSS
A5
A1
A4
A2
A3
n.c.
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1
November 01, 2001