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UL635H256TC55 PDF预览

UL635H256TC55

更新时间： 2024-11-09 04:02:43
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器光电二极管
页数 文件大小 规格书
13页 205K
描述
Non-Volatile SRAM, 32KX8, 55ns, CMOS, PDSO32, TSOP1-32

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UL635H256TC55 数据手册

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UL635H256  
Advanced Information  
Low Voltage PowerStore 32K x 8 nvSRAM  
Description  
Features  
automatically on power up. The  
UL635H256 combines the high per-  
formance and ease of use of a fast  
SRAM with nonvolatile data inte-  
grity.  
STORE cycles also may be initiated  
under user control via a software  
sequence.  
Once a STORE cycle is initiated,  
further input or output are disabled  
until the cycle is completed.  
Because a sequence of addresses  
is used for STORE initiation, it is  
important that no other read or write  
accesses intervene in the sequence  
or the sequence will be aborted.  
RECALL cycles may also be initia-  
ted by a software sequence.  
Internally, RECALL is a two step  
procedure. First, the SRAM data is  
cleared and second, the nonvolatile  
information is transferred into the  
SRAM cells.  
The RECALL operation in no way  
alters the data in the EEPROM  
cells. The nonvolatile data can be  
recalled an unlimited number of  
times.  
The UL635H256 has two separate  
modes of operation: SRAM mode  
and nonvolatile mode. In SRAM  
mode, the memory operates as an  
ordinary static RAM. In nonvolatile  
operation, data is transferred in  
parallel from SRAM to EEPROM or  
from EEPROM to SRAM. In this  
mode SRAM functions are disab-  
led.  
The UL635H256 is a fast static  
RAM (45 and 55 ns), with a nonvo-  
latile electrically erasable PROM  
(EEPROM) element incorporated  
in each static memory cell. The  
SRAM can be read and written an  
unlimited number of times, while  
independent nonvolatile data resi-  
des in EEPROM. Data transfers  
from the SRAM to the EEPROM  
(the STORE operation) take place  
automatically upon power down  
using charge stored in system  
capacitance. Transfers from the  
EEPROM to the SRAM (the  
RECALL operation) take place  
High-performance CMOS non-  
volatile static RAM 32768 x 8 bits  
45 and 55 ns Access Times  
20 and 25 ns Output Enable  
Access Times  
ICC = 8 mA at 200 ns Cycle Time  
Automatic STORE to EEPROM  
on Power Down using system  
capacitance  
Software initiated STORE  
Automatic STORE Timing  
105 STORE cycles to EEPROM  
10 years data retention in  
EEPROM  
Automatic RECALL on Power Up  
Software RECALL Initiation  
Unlimited RECALL cycles from  
EEPROM  
Wide voltage range: 2.7 ... 3.6 V  
Operating temperature range:  
0 to 70 °C  
-40 to 85 °C  
CECC 90000 Quality Standard  
ESD characterization according  
MIL STD 883C M3015.7-HBM  
Packages: SOP28 (330 mil)  
TSOP32 (Type I)  
Pin Configuration  
Pin Description  
G
A11  
A9  
1
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
n.c.  
A10  
E
VCC  
W
A13  
A8  
A9  
A11  
G
A10  
E
DQ7  
DQ6  
DQ5  
DQ4  
DQ3  
A14  
A12  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
1
2
3
4
5
6
7
8
9
10  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
Signal Name Signal Description  
2
3
A0 - A14  
Address Inputs  
Data In/Out  
A8  
4
DQ7  
DQ6  
DQ5  
DQ4  
DQ3  
VSS  
DQ2  
DQ1  
DQ0  
A0  
A13  
W
n. c.  
VCC  
n. c.  
A14  
A12 11  
A7  
A6  
5
DQ0 - DQ7  
6
7
Chip Enable  
E
8
SOP  
TSOP  
9
Output Enable  
Write Enable  
Power Supply Voltage  
Ground  
G
10  
W
12  
13  
DQ0 11  
DQ1  
DQ2 13  
VSS  
VCC  
VSS  
12  
A5 14  
A4  
A3  
A1  
15  
16  
A2  
14  
n.c.  
Top View  
Top View  
271  
December 12, 1997  
1234567...13

中文翻译

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