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Datasheet > UL635H256SK55G1
UL635H256SK55G1 PDF预览

UL635H256SK55G1

更新时间： 2024-09-20 15:55:59
品牌 Logo 应用领域
SIMTEK 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
13页 137K
描述
Non-Volatile SRAM, 32KX8, 55ns, CMOS, PDSO28, 0.330 INCH, SOP1-28

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中文翻译

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UL635H256SK55G1 技术参数

生命周期：Obsolete包装说明：SOP,
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.41风险等级：5.74
最长访问时间：55 nsJESD-30 代码：R-PDSO-G28
JESD-609代码：e3长度：18.1 mm
内存密度：262144 bit内存集成电路类型：NON-VOLATILE SRAM
内存宽度：8功能数量：1
端子数量：28字数：32768 words
字数代码：32000工作模式：ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：32KX8封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE并行/串行：PARALLEL
峰值回流温度（摄氏度）：NOT SPECIFIED认证状态：Not Qualified
座面最大高度：2.54 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：MATTE TIN
端子形式：GULL WING端子节距：1.27 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：8.75 mmBase Number Matches：1

UL635H256SK55G1 数据手册

 浏览型号UL635H256SK55G1的Datasheet PDF文件第2页浏览型号UL635H256SK55G1的Datasheet PDF文件第3页浏览型号UL635H256SK55G1的Datasheet PDF文件第4页浏览型号UL635H256SK55G1的Datasheet PDF文件第5页浏览型号UL635H256SK55G1的Datasheet PDF文件第6页浏览型号UL635H256SK55G1的Datasheet PDF文件第7页 
UL635H256  
Low Voltage PowerStore 32K x 8 nvSRAM  
Features  
Description  
F High-performance CMOS non-  
The UL635H256 has two separate The UL635H256 combines the  
volatile static RAM 32768 x 8 bits modes of operation: SRAM mode high performance and ease of use  
F 35, 45 and 55 ns Access Times  
F 15, 20 and 25 ns Output Enable  
Access Times  
F ICC = 8 mA at 200 ns Cycle Time  
F Automatic STORE to EEPROM  
on Power Down using system  
capacitance  
and nonvolatile mode. In SRAM of a fast SRAM with nonvolatile  
mode, the memory operates as an data integrity.  
ordinary static RAM. In nonvolatile STORE cycles also may be initia-  
operation, data is transferred in ted under user control via a soft-  
parallel from SRAM to EEPROM or ware sequence.  
from EEPROM to SRAM. In this Once a STORE cycle is initiated,  
mode SRAM functions are disab- further input or output are disabled  
F Software initiated STORE  
F Automatic STORE Timing  
F 105 STORE cycles to EEPROM  
F 10 years data retention in  
EEPROM  
led.  
until the cycle is completed.  
The UL635H256 is a fast static Because a sequence of addresses  
RAM (35, 45 and 55 ns), with a is used for STORE initiation, it is  
nonvolatile electrically erasable important that no other read or  
PROM (EEPROM) element incor- write accesses intervene in the  
F Automatic RECALL on Power Up porated in each static memory cell. sequence or the sequence will be  
F Software RECALL Initiation  
F Unlimited RECALL cycles from  
EEPROM  
F Wide voltage range: 2.7 ... 3.6 V  
(3.0 ... 3.6 V for 35 ns type)  
F Operating temperature range:  
0 to 70 °C  
The SRAM can be read and written aborted.  
an unlimited number of times, while RECALL cycles may also be initia-  
independent nonvolatile data resi- ted by a software sequence.  
des in EEPROM. Data transfers Internally, RECALL is a two step  
from the SRAM to the EEPROM procedure. First, the SRAM data is  
(the STORE operation) take place cleared and second, the nonvola-  
automatically upon power down tile information is transferred into  
-40 to 85 °C (only 45 and 55 ns) using charge stored in system the SRAM cells.  
F CECC 90000 Quality Standard  
F ESD protection > 2000 V  
(MIL STD 883C M3015.7-HBM)  
F Packages: SOP28 (330 mil)  
TSOP32 (Type I)  
capacitance. Transfers from the The RECALL operation in no way  
EEPROM to the SRAM (the alters the data in the EEPROM  
RECALL operation) take place cells. The nonvolatile data can be  
automatically on powerup.  
recalled an unlimited number of  
times.  
Pin Description  
Pin Configuration  
G
A11  
A9  
A8  
A13  
W
1
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
n.c.  
A10  
E
VCC  
W
A13  
A8  
A9  
A11  
G
A10  
E
DQ7  
DQ6  
DQ5  
DQ4  
DQ3  
A14  
A12  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
1
2
3
4
5
6
7
8
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
2
Signal Name Signal Description  
3
4
DQ7  
DQ6  
DQ5  
DQ4  
DQ3  
VSS  
DQ2  
DQ1  
DQ0  
A0  
A0 - A14  
Address Inputs  
Data In/Out  
5
6
DQ0 - DQ7  
n. c.  
VCC  
n. c.  
A14  
A12  
A7  
7
8
SOP  
TSOP  
Chip Enable  
E
9
10  
11  
12  
13  
14  
15  
16  
9
Output Enable  
Write Enable  
Power Supply Voltage  
Ground  
G
A0  
10  
11  
12  
13  
14  
DQ0  
DQ1  
DQ2  
VSS  
W
A6  
A5  
A1  
VCC  
VSS  
A4  
A2  
A3  
n.c.  
Top View  
Top View  
1
September 25, 2002  
1234567...13

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