Datasheet > 微控制器和处理器 > 串行 IO/通信控制器> TSB12LV21AIPGF

TSB12LV21AIPGF

更新时间： 2024-09-16 13:02:03

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
38页	523K
描述
PCILynx - PCI to 1394 3.3V Link Layer with 32-bit PCI I/F, 1K FIFOs 176-LQFP -40 to 85

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TSB12LV21AIPGF 技术参数

是否无铅：	含铅	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	LFQFP,
针数：	176	Reach Compliance Code：	unknown
HTS代码：	8542.31.00.01	Factory Lead Time：	1 week
风险等级：	5.77	其他特性：	ALSO REQUIRES 5V SUPPLY
地址总线宽度：	32	边界扫描：	NO
总线兼容性：	PCI	最大时钟频率：	50 MHz
最大数据传输速率：	50 MBps	外部数据总线宽度：	32
JESD-30 代码：	S-PQFP-G176	长度：	24 mm
低功率模式：	NO	串行 I/O 数：	1
端子数量：	176	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	PLASTIC/EPOXY
封装代码：	LFQFP	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE, FINE PITCH	认证状态：	Not Qualified
座面最大高度：	1.6 mm	最大供电电压：	3.6 V
最小供电电压：	3 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
宽度：	24 mm	uPs/uCs/外围集成电路类型：	SERIAL IO/COMMUNICATION CONTROLLER, LAN
Base Number Matches：	1

TSB12LV21AIPGF 数据手册

TSB21LV03

IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER

SLLS230A – MARCH 1996 – REVISED DECEMBER 1996

Supports Provisions of IEEE 1394-1995

Standard for High Performance Serial Bus

Data Interface to Link-Layer Controller

Provided Through 2/4 Parallel Lines at

50 Mbits/s

†

Fully Interoperable with FireWire

Implementation of IEEE 1394-1995

25-MHz Crystal Oscillator and PLL Provide

Transmit/Receive Data at 100/200 Mbits/s,

and Link-Layer Controller Clock at 50 MHz

Provides Three Fully Compliant Cable

Ports at 100/200 Megabits per Second

(Mbits/s)

Interoperable with 1394 Link-Layer

Controllers Using 5-V Supplies

Cable Ports Monitor Line Conditions for

Active Connection to Remote Node

Interoperable Across 1394 Cable with 1394

Physical Layers (Phy) Using 5-V Supplies

Device Power-Down Feature to Conserve

Energy in Battery-Powered Applications

Node Power-Class Information Signaling

for System Power Management

Inactive Ports Disabled to Save Power

Cable Power Presence Monitoring

Logic Performs System Initialization and

Arbitration Functions

Separate Cable Bias and Driver Termination

Voltage Supply for Each Port

Encode and Decode Functions Included for

Data-Strobe Bit-Level Encoding

Multiple Separate Package Terminals

Provided for Analog and Digital Supplies

and Grounds

Incoming Data Resynchronized to Local

Clock

High Performance 64-Pin TQFP (PM)

Package

Single 3.3-V Supply Operation

Interface to Link-Layer Controller Supports

Optional Annex J Electrical Isolation and

TI Bus-Holder Isolation

description

The TSB21LV03 provides the analog physical layer functions needed to implement a three-port node in a

cable-based IEEE 1394-1995 network. Each cable port incorporates two differential line transceivers. The

transceivers include circuitry to monitor the line conditions as needed for determining connection status, for

initializationandarbitration, andforpacketreceptionandtransmission. TheTSB21LV03isdesignedtointerface

with a link-layer controller (LLC), such as the TSB12LV21, TSB12LV31, or TSB12C01A.

The TSB21LV03 requires either an external 24.576-MHz crystal or crystal oscillator. The internal oscillator

drives an internal phase-locked loop (PLL), which generates the required 196.608-MHz reference signal. The

196.608-MHz reference signal is internally divided to provide the 49.152/98.304-MHz clock signals that control

transmission of the outbound encoded strobe and data information. The 49.152-MHz clock signal is also

supplied to the associated LLC for synchronization of the two chips and is used for resynchronization of the

received data. The power-down function, when enabled by taking the PD terminal high, stops operation of the

PLL and disables all circuitry except the cable-not-active signal circuitry.

The TSB21LV03 supports an optional isolation barrier between itself and its LLC. When ISO is tied high, the

link interface outputs behave normally. When ISO is tied low, internal differentiating logic is enabled, and the

outputs become short pulses, which can be coupled through a capacitor or transformer as described in the IEEE

1394-1995 Annex J.

†

This serial bus implements technology covered by one or more patents of Apple Computer, Incorporated and INMOS, Limited.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

FireWire is a trademark of Apple Computer, Incorporated.

TI is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7...38

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与TSB12LV21AIPGF相关器件

型号	品牌	获取价格	描述	数据表
TSB12LV21AMPGF	TI	获取价格	PCILynx - PCI to 1394 3.3V Link Layer with 32-bit PCI I/F, 1K FIFOs 176-LQFP -55 to 125
TSB12LV21APGF	TI	获取价格	IEEE 1394-1995 BUS TO PCI BUS INTERFACE
TSB12LV21B	TI	获取价格	IEEE 1394 LINK LAYER CONTROLLER
TSB12LV21B-EP	TI	获取价格	(PCILynx-2) IEEE 1394 LINK LAYER CONTROLLER
TSB12LV21BMPGF	TI	获取价格	暂无描述
TSB12LV21BMPGFEP	TI	获取价格	(PCILynx-2) IEEE 1394 LINK LAYER CONTROLLER
TSB12LV21BPGF	TI	获取价格	IEEE 1394 LINK LAYER CONTROLLER
TSB12LV21BPGFG4	TI	获取价格	PCILynx - PCI to 1394 3.3V Link Layer with 32-bit PCI I/F, 4K FIFOs 176-LQFP
TSB12LV21PGF	TI	获取价格	PCILynx - 1394 to PCI Link Layer Controller 176-LQFP
TSB12LV22	TI	获取价格	OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER

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