Datasheet > TSB12LV26I

TSB12LV26I

更新时间： 2024-11-27 01:13:27

品牌	Logo	应用领域
德州仪器 - TI		PC
页数	文件大小	规格书
5页	62K
描述
OHCI-Lynx PCI-Based IEEE 1394 Host Controller

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TSB12LV26I 数据手册

TSB12LV26

TSB12LV26I

www.ti.com

SLLA214–JUNE 2006

OHCI-Lynx™ PCI-Based IEEE 1394 Host Controller

FEATURES

•

External cycle timer control for customized

synchronization

•

3.3-V and 5-V PCI bus signaling

•

PCI burst transfers and deep FIFOs to

tolerate large host latency

•

3.3-V supply (core voltage is internally

regulated to 1.8 V)

•

Two general-purpose I/Os

•

Serial bus data rates of 100M bits/s, 200M

bits/s, and 400M bits/s

Fabricated in advanced low-power CMOS

process

Physical write posting of up to three

outstanding transactions

•

Packaged in 100-terminal LQFP (PZT)

PCI_CLKRUN protocol

Serial ROM interface supports 2-wire devices

DESCRIPTION

The Texas Instruments TSB12LV26 device is a PCI-to-1394 host controller compliant with the PCI Local Bus

Specification, PCI Bus Power Management Interface Specification, IEEE Std 1394-1995, and 1394 Open Host

Controller Interface Specification. The chip provides the IEEE 1394 link function and is compatible with 100M

bits/s, 200M bits/s, and 400M bits/s serial bus data rates.

As required by the 1394 Open Host Controller Interface Specification (OHCI) and IEEE Std 1394a-2000, internal

control registers are memory-mapped and nonprefetchable. The PCI configuration header is accessed through

configuration cycles specified by PCI and provides plug-and-play (PnP) compatibility. Furthermore, the

TSB12LV26 device is compliant with the PCI Bus Power Management Interface Specification, per the PC 99

Design Guide requirements. TSB12LV26 device supports the D0, D2, and D3 power states.

The TSB12LV26 design provides PCI bus master bursting and is capable of transferring a cacheline of data at

132M bytes/s after connection to the memory controller. Since PCI latency can be large, deep FIFOs are

provided to buffer 1394 data.

The TSB12LV26 device provides physical write posting buffers and a highly-tuned physical data path for SBP-2

performance. The TSB12LV26 device also provides multiple isochronous contexts, multiple cacheline burst

transfers, advanced internal arbitration, and bus-holding buffers on the PHY/link interface.

An advanced CMOS process achieves low power consumption and allows the TSB12LV26 device to operate at

PCI clock rates up to 33 MHz.

NOTE:

This product is for high-volume PC applications only. For a complete datasheet or

more information contact support@ti.com.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

OHCI-Lynx is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5

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与TSB12LV26I相关器件

型号	品牌	获取价格	描述	数据表
TSB12LV26IPZT	TI	获取价格	IC I2C BUS CONTROLLER, PQFP100, PLASTIC, LQFP-100, Serial IO/Communication Controller
TSB12LV26IPZTEP	TI	获取价格	暂无描述
TSB12LV26PZ	TI	获取价格	OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER
TSB12LV26PZT	TI	获取价格	OHCI-Lynx PCI-Based IEEE 1394 Host Controller
TSB12LV26PZTG4	TI	获取价格	OHCI-Lynx PCI-Based IEEE 1394 Host Controller
TSB12LV26TPZEP	TI	获取价格	OHCI-LYNX PCI-BASED IEEE 1394 HOST CONTROLLER
TSB12LV31	TI	获取价格	IEEE 1394-1995 General-Purpose Link-Layer Controller
TSB12LV31IPZ	TI	获取价格	GPLynx - General Purpose 1394 3.3V Link Layer with 8/16 bit I/F, 200byte FIFOs w/ Isochron
TSB12LV31IWN	TI	获取价格	1 CHANNEL(S), 200Mbps, SERIAL COMM CONTROLLER, CQFP100, CERAMIC, QFP-100
TSB12LV31MWN	TI	获取价格	1 CHANNEL(S), 200Mbps, SERIAL COMM CONTROLLER, CQFP100, CERAMIC, QFP-100

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