5秒后页面跳转
TSB12LV21PGF PDF预览

TSB12LV21PGF

更新时间: 2024-11-06 13:14:55
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
38页 523K
描述
PCILynx - 1394 to PCI Link Layer Controller 176-LQFP

TSB12LV21PGF 技术参数

是否无铅: 含铅生命周期:Obsolete
零件包装代码:QFP包装说明:LFQFP,
针数:176Reach Compliance Code:unknown
ECCN代码:3A991.A.2HTS代码:8542.31.00.01
风险等级:5.68地址总线宽度:32
最大时钟频率:33 MHz最大数据传输速率:50 MBps
驱动器接口标准:IEEE 1394外部数据总线宽度:32
JESD-30 代码:S-PQFP-G176长度:24 mm
端子数量:176封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH认证状态:Not Qualified
座面最大高度:1.6 mm最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD宽度:24 mm
uPs/uCs/外围集成电路类型:BUS CONTROLLER, PCIBase Number Matches:1

TSB12LV21PGF 数据手册

 浏览型号TSB12LV21PGF的Datasheet PDF文件第2页浏览型号TSB12LV21PGF的Datasheet PDF文件第3页浏览型号TSB12LV21PGF的Datasheet PDF文件第4页浏览型号TSB12LV21PGF的Datasheet PDF文件第5页浏览型号TSB12LV21PGF的Datasheet PDF文件第6页浏览型号TSB12LV21PGF的Datasheet PDF文件第7页 
TSB21LV03  
IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER  
SLLS230A – MARCH 1996 – REVISED DECEMBER 1996  
Supports Provisions of IEEE 1394-1995  
Standard for High Performance Serial Bus  
Data Interface to Link-Layer Controller  
Provided Through 2/4 Parallel Lines at  
50 Mbits/s  
Fully Interoperable with FireWire  
Implementation of IEEE 1394-1995  
25-MHz Crystal Oscillator and PLL Provide  
Transmit/Receive Data at 100/200 Mbits/s,  
and Link-Layer Controller Clock at 50 MHz  
Provides Three Fully Compliant Cable  
Ports at 100/200 Megabits per Second  
(Mbits/s)  
Interoperable with 1394 Link-Layer  
Controllers Using 5-V Supplies  
Cable Ports Monitor Line Conditions for  
Active Connection to Remote Node  
Interoperable Across 1394 Cable with 1394  
Physical Layers (Phy) Using 5-V Supplies  
Device Power-Down Feature to Conserve  
Energy in Battery-Powered Applications  
Node Power-Class Information Signaling  
for System Power Management  
Inactive Ports Disabled to Save Power  
Cable Power Presence Monitoring  
Logic Performs System Initialization and  
Arbitration Functions  
Separate Cable Bias and Driver Termination  
Voltage Supply for Each Port  
Encode and Decode Functions Included for  
Data-Strobe Bit-Level Encoding  
Multiple Separate Package Terminals  
Provided for Analog and Digital Supplies  
and Grounds  
Incoming Data Resynchronized to Local  
Clock  
High Performance 64-Pin TQFP (PM)  
Package  
Single 3.3-V Supply Operation  
Interface to Link-Layer Controller Supports  
Optional Annex J Electrical Isolation and  
TI Bus-Holder Isolation  
description  
The TSB21LV03 provides the analog physical layer functions needed to implement a three-port node in a  
cable-based IEEE 1394-1995 network. Each cable port incorporates two differential line transceivers. The  
transceivers include circuitry to monitor the line conditions as needed for determining connection status, for  
initializationandarbitration, andforpacketreceptionandtransmission. TheTSB21LV03isdesignedtointerface  
with a link-layer controller (LLC), such as the TSB12LV21, TSB12LV31, or TSB12C01A.  
The TSB21LV03 requires either an external 24.576-MHz crystal or crystal oscillator. The internal oscillator  
drives an internal phase-locked loop (PLL), which generates the required 196.608-MHz reference signal. The  
196.608-MHz reference signal is internally divided to provide the 49.152/98.304-MHz clock signals that control  
transmission of the outbound encoded strobe and data information. The 49.152-MHz clock signal is also  
supplied to the associated LLC for synchronization of the two chips and is used for resynchronization of the  
received data. The power-down function, when enabled by taking the PD terminal high, stops operation of the  
PLL and disables all circuitry except the cable-not-active signal circuitry.  
The TSB21LV03 supports an optional isolation barrier between itself and its LLC. When ISO is tied high, the  
link interface outputs behave normally. When ISO is tied low, internal differentiating logic is enabled, and the  
outputs become short pulses, which can be coupled through a capacitor or transformer as described in the IEEE  
1394-1995 Annex J.  
This serial bus implements technology covered by one or more patents of Apple Computer, Incorporated and INMOS, Limited.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
FireWire is a trademark of Apple Computer, Incorporated.  
TI is a trademark of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

与TSB12LV21PGF相关器件

型号 品牌 获取价格 描述 数据表
TSB12LV22 TI

获取价格

OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER
TSB12LV22PZP TI

获取价格

OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER
TSB12LV23 TI

获取价格

TSB12LV23 OHCI-Lynx PCI-Based IEEE 1394 Host Controller
TSB12LV23A TI

获取价格

IC,BUS CONTROLLER,CMOS,QFP,100PIN
TSB12LV23APZT TI

获取价格

IEEE 1394-1995, 1394a Serial Link Layer Controller 100-TQFP 0 to 70
TSB12LV23PZ TI

获取价格

TSB12LV23 OHCI-Lynx PCI-Based IEEE 1394 Host Controller
TSB12LV23PZR TI

获取价格

PCI BUS CONTROLLER, PQFP100, PLASTIC, QFP-100
TSB12LV26 TI

获取价格

OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER
TSB12LV26-EP TI

获取价格

OHCI-LYNX PCI-BASED IEEE 1394 HOST CONTROLLER
TSB12LV26-EP_14 TI

获取价格

OHCI-Lynx PCI-Based IEEE 1394 Host controller