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TSB12LV26PZTG4 PDF预览

TSB12LV26PZTG4

更新时间： 2024-09-17 01:13:27
品牌 Logo 应用领域
德州仪器 - TI 时钟数据传输PC驱动外围集成电路驱动器
页数 文件大小 规格书
5页 62K
描述
OHCI-Lynx PCI-Based IEEE 1394 Host Controller

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TSB12LV26PZTG4 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：QFP包装说明：TFQFP,
针数：100Reach Compliance Code：compliant
HTS代码：8542.31.00.01风险等级：5.75
最大时钟频率：33 MHz最大数据传输速率：132 MBps
驱动器接口标准：IEEE 1394JESD-30 代码：S-PQFP-G100
JESD-609代码：e4长度：14 mm
湿度敏感等级：4端子数量：100
封装主体材料：PLASTIC/EPOXY封装代码：TFQFP
封装形状：SQUARE封装形式：FLATPACK, THIN PROFILE, FINE PITCH
座面最大高度：1.2 mm标称供电电压：3.3 V
表面贴装：YES技术：CMOS
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
宽度：14 mmuPs/uCs/外围集成电路类型：BUS CONTROLLER, PCI
Base Number Matches：1

TSB12LV26PZTG4 数据手册

 浏览型号TSB12LV26PZTG4的Datasheet PDF文件第2页浏览型号TSB12LV26PZTG4的Datasheet PDF文件第3页浏览型号TSB12LV26PZTG4的Datasheet PDF文件第4页浏览型号TSB12LV26PZTG4的Datasheet PDF文件第5页 
TSB12LV26  
TSB12LV26I  
www.ti.com  
SLLA214–JUNE 2006  
OHCI-Lynx™ PCI-Based IEEE 1394 Host Controller  
FEATURES  
•
External cycle timer control for customized  
synchronization  
•
3.3-V and 5-V PCI bus signaling  
•
PCI burst transfers and deep FIFOs to  
tolerate large host latency  
•
3.3-V supply (core voltage is internally  
regulated to 1.8 V)  
•
•
Two general-purpose I/Os  
•
•
•
Serial bus data rates of 100M bits/s, 200M  
bits/s, and 400M bits/s  
Fabricated in advanced low-power CMOS  
process  
Physical write posting of up to three  
outstanding transactions  
•
•
Packaged in 100-terminal LQFP (PZT)  
PCI_CLKRUN protocol  
Serial ROM interface supports 2-wire devices  
DESCRIPTION  
The Texas Instruments TSB12LV26 device is a PCI-to-1394 host controller compliant with the PCI Local Bus  
Specification, PCI Bus Power Management Interface Specification, IEEE Std 1394-1995, and 1394 Open Host  
Controller Interface Specification. The chip provides the IEEE 1394 link function and is compatible with 100M  
bits/s, 200M bits/s, and 400M bits/s serial bus data rates.  
As required by the 1394 Open Host Controller Interface Specification (OHCI) and IEEE Std 1394a-2000, internal  
control registers are memory-mapped and nonprefetchable. The PCI configuration header is accessed through  
configuration cycles specified by PCI and provides plug-and-play (PnP) compatibility. Furthermore, the  
TSB12LV26 device is compliant with the PCI Bus Power Management Interface Specification, per the PC 99  
Design Guide requirements. TSB12LV26 device supports the D0, D2, and D3 power states.  
The TSB12LV26 design provides PCI bus master bursting and is capable of transferring a cacheline of data at  
132M bytes/s after connection to the memory controller. Since PCI latency can be large, deep FIFOs are  
provided to buffer 1394 data.  
The TSB12LV26 device provides physical write posting buffers and a highly-tuned physical data path for SBP-2  
performance. The TSB12LV26 device also provides multiple isochronous contexts, multiple cacheline burst  
transfers, advanced internal arbitration, and bus-holding buffers on the PHY/link interface.  
An advanced CMOS process achieves low power consumption and allows the TSB12LV26 device to operate at  
PCI clock rates up to 33 MHz.  
NOTE:  
This product is for high-volume PC applications only. For a complete datasheet or  
more information contact support@ti.com.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
OHCI-Lynx is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2006, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
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