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TSB11LV01PT PDF预览

TSB11LV01PT

更新时间: 2024-09-14 22:10:03
品牌 Logo 应用领域
德州仪器 - TI /
页数 文件大小 规格书
21页 321K
描述
3-V 1-PORT IEEE 1394-1995 CABLE TRANSCEIVER/ARBITER

TSB11LV01PT 数据手册

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TSB11LV01  
3-V 1-PORT IEEE 1394-1995 CABLE TRANSCEIVER/ARBITER  
SLLS232B – MARCH 1996 – REVISED MAY 1997  
Supports Provisions of IEEE 1394-1995  
Standard for High Performance Serial Bus  
Data Interface to Link Layer Controller  
(Link) Provided Through Two Parallel  
Signal Lines at 50 Mbits/s  
Fully Interoperable With FireWire  
Implementation of IEEE 1394-1995  
25-MHz Crystal Oscillator and PLL Provide  
Transmit, Receive Data, and Link Layer  
Controller Clocks at 50 MHz  
Provides A Single Fully-Compliant Cable  
Port at 100 Megabits per Second (Mbits/s)  
Digital I/Os are 5 V tolerant  
Cable Port Monitors Line Conditions for  
Active Connection to a Remote Node  
Node Power Class Information Signaling  
for System Power Management  
Inactive Port Disabled to Save Power  
Cable Power Presence Monitoring  
Cable Inactivity Monitor Output and  
Power-down Input Provided for Additional  
Sleep-Mode Power Savings  
Cable Bias and Driver Termination Voltage  
Supply  
Internal Bandgap Reference Provided for  
Setting Stable Operating Bias Conditions  
Single 3-V Supply Operation  
Separate Multiple Package Terminals  
Provided for Analog and Digital Supplies  
and Grounds  
Logic Performs System Initialization and  
Arbitration Functions  
Encode and Decode Functions Included for  
Data-Strobe Bit-Level Encoding  
High Performance 48-Pin TQFP (PT)  
Package  
Incoming Data Resynchronized to Local  
Clock  
description  
The TSB11LV01 provides the analog transceiver functions needed to implement a single port node in a cable  
based IEEE 1394-1995 network. The cable port incorporates two differential line transceivers. The transceivers  
include circuitry to monitor the line conditions as needed for determining connection status, for initialization and  
arbitration, and for packet reception and transmission. The TSB11LV01 is designed to interface with a link layer  
controller, such as the TSB12C01A.  
The TSB11LV01 requires an external 24.576-MHz crystal, which drives an internal phase-locked loop (PLL)  
generating the required 98.304-MHz reference signal. The 98.304-MHz reference signal is internally divided  
to provide the 49.152-MHz ±100 ppm system clock signals that control transmission of the outbound encoded  
strobe and data information. The 49.152-MHz clock signal is also supplied to the associated link for  
synchronization of the two chips and is used for resynchronization of the received data. The power-down  
function, when enabled by asserting the PWRDN terminal high, stops operation of the PLL.  
Data bits to be transmitted are received from the link on two parallel paths and are latched internally in the  
TSB11LV01 in synchronization with the 49.152-MHz system clock. These bits are combined serially, encoded,  
and transmitted at 98.304-Mbits/s as the outbound data-strobe information stream. During transmit, the  
encoded data information is transmitted differentially on the TPB cable pair, and the encoded strobe information  
is transmitted differentially on the TPA cable pair.  
NOTE  
In this document, phy is the physical layer and link is the link layer controller.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thomson, Limited.  
FireWire is a trademark of Apple Computer, Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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