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TP0610T-G PDF预览

TP0610T-G

更新时间: 2024-11-15 21:15:03
品牌 Logo 应用领域
超科 - SUPERTEX 开关光电二极管晶体管
页数 文件大小 规格书
5页 599K
描述
Small Signal Field-Effect Transistor, 0.12A I(D), 60V, 1-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, TO-236AB, 2.90 X 1.30 MM, 1.12 MM HEIGHT, GREEN PACKAGE-3

TP0610T-G 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:SOT-23
包装说明:SMALL OUTLINE, R-PDSO-G3针数:3
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8541.21.00.95风险等级:7.27
其他特性:LOW THRESHOLD配置:SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压:60 V最大漏极电流 (ID):0.12 A
最大漏源导通电阻:10 ΩFET 技术:METAL-OXIDE SEMICONDUCTOR
最大反馈电容 (Crss):10 pFJEDEC-95代码:TO-236AB
JESD-30 代码:R-PDSO-G3JESD-609代码:e3
湿度敏感等级:1元件数量:1
端子数量:3工作模式:ENHANCEMENT MODE
最高工作温度:150 °C封装主体材料:PLASTIC/EPOXY
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED极性/信道类型:P-CHANNEL
最大功率耗散 (Abs):0.36 W认证状态:Not Qualified
子类别:Other Transistors表面贴装:YES
端子面层:MATTE TIN端子形式:GULL WING
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
晶体管应用:SWITCHING晶体管元件材料:SILICON
Base Number Matches:1

TP0610T-G 数据手册

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Supertex inc.  
TP0610T  
P-Channel Enhancement Mode  
Vertical DMOS FETs  
Features  
General Description  
High input impedance and high gain  
Low power drive requirement  
Ease of paralleling  
This low threshold enhancement-mode (normally-off) transistor  
utilizes a vertical DMOS structure and Supertex’s well-proven  
silicon-gate manufacturing process. This combination produces a  
device with the power handling capabilities of bipolar transistors  
and with the high input impedance and positive temperature  
coefficient inherent in MOS devices. Characteristic of all MOS  
structures, this device is free from thermal runaway and thermally-  
induced secondary breakdown.  
Low CISS and fast switching speeds  
Excellent thermal stability  
Integral source-drain diode  
Free from secondary breakdown  
Applications  
Supertex’s vertical DMOS FETs are ideally suited to a wide range  
of switching and amplifying applications where very low threshold  
voltage, high breakdown voltage, high input impedance, low input  
capacitance, and fast switching speeds are desired.  
Logic level interfaces - ideal for TTL and CMOS  
Solid state relays  
Battery operated systems  
Photo voltaic systems  
Analog switches  
Power management  
Telecom switches  
Ordering Information  
RDS(ON)  
ID(ON)  
Package Options  
BVDSS/BVDGS  
Device  
(max)  
(Ω)  
(min)  
(mA)  
(V)  
TO-236AB (SOT-23)  
TP0610T  
TP0610T-G  
-60  
10  
-50  
For packaged products, -G indicates package is RoHS compliant (‘Green’).  
Consult factory for die / wafer form part numbers.  
Refer to Die Specification VF21 for layout and dimensions.  
Absolute Maximum Ratings  
Pin Configuration  
Parameter  
Value  
BVDSS  
BVDGS  
±20V  
DRAIN  
Drain-to-source voltage  
Drain-to-gate voltage  
Gate-to-source voltage  
SOURCE  
Operating and storage temperature  
-55OC to +150OC  
GATE  
Absolute Maximum Ratings are those values beyond which damage to the device  
may occur. Functional operation under these conditions is not implied. Continuous  
operation of the device at the absolute rating level may affect device reliability. All  
voltages are referenced to device ground.  
TO-236AB (SOT-23) (T)  
Product Marking  
W = Code for week sealed  
= “Green” Packaging  
T50W  
Package may or may not include the following marks: Si or  
TO-236AB (SOT-23) (T)  
Supertex inc. 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com  

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