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TP0620N3-GP002 PDF预览

TP0620N3-GP002

更新时间： 2024-02-08 16:23:13
品牌 Logo 应用领域
超科 - SUPERTEX 输入元件开关晶体管
页数 文件大小 规格书
5页 603K
描述
Small Signal Field-Effect Transistor,

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TP0620N3-GP002 技术参数

是否Rohs认证： 符合生命周期：Transferred
包装说明：CYLINDRICAL, O-PBCY-T3Reach Compliance Code：unknown
风险等级：5.63其他特性：HIGH INPUT IMPEDANCE, LOGIC LEVEL COMPATIBLE
配置：SINGLE WITH BUILT-IN DIODE最小漏源击穿电压：200 V
最大漏极电流 (ID)：0.175 A最大漏源导通电阻：12 Ω
FET 技术：METAL-OXIDE SEMICONDUCTOR最大反馈电容 (Crss)：35 pF
JEDEC-95代码：TO-92JESD-30 代码：O-PBCY-T3
元件数量：1端子数量：3
工作模式：ENHANCEMENT MODE最高工作温度：150 °C
最低工作温度：-55 °C封装主体材料：PLASTIC/EPOXY
封装形状：ROUND封装形式：CYLINDRICAL
极性/信道类型：P-CHANNEL功耗环境最大值：1 W
最大功率耗散 (Abs)：1 W表面贴装：NO
端子形式：THROUGH-HOLE端子位置：BOTTOM
晶体管应用：SWITCHING晶体管元件材料：SILICON
Base Number Matches：1

TP0620N3-GP002 数据手册

 浏览型号TP0620N3-GP002的Datasheet PDF文件第2页浏览型号TP0620N3-GP002的Datasheet PDF文件第3页浏览型号TP0620N3-GP002的Datasheet PDF文件第4页浏览型号TP0620N3-GP002的Datasheet PDF文件第5页 
TP0620  
Supertex inc.  
P-Channel Enhancement-Mode  
Vertical DMOS FET  
Features  
General Description  
► Low threshold (-2.4V max.)  
► High input impedance  
► Low input capacitance (85pF typical)  
► Fast switching speeds  
► Low on-resistance  
This low threshold, enhancement-mode (normally-off)  
transistor utilizes a vertical DMOS structure and Supertex’s  
well-proven, silicon-gate manufacturing process. This  
combination produces a device with the power handling  
capabilities of bipolar transistors and the high input impedance  
and positive temperature coefficient inherent in MOS devices.  
Characteristic of all MOS structures, this device is free  
from thermal runaway and thermally-induced secondary  
breakdown.  
► Free from secondary breakdown  
► Low input and output leakage  
Applications  
► Logic level interfaces - ideal for TTL and CMOS  
Supertex’s vertical DMOS FETs are ideally suited to a wide  
range of switching and amplifying applications where very  
low threshold voltage, high breakdown voltage, high input  
impedance, low input capacitance, and fast switching speeds  
are desired.  
► Solid state relays  
► Battery operated systems  
► Photo voltaic drives  
► Analog switches  
► General purpose line drivers  
► Telecom switches  
Ordering Information  
Product Summary  
RDS(ON)  
ID(ON)  
Part Number  
Package Option  
Packing  
VGS(th)  
(max)  
BVDSS/BVDGS  
(max)  
(min)  
TP0620N3-G  
3-Lead TO-92  
1000/Bag  
-200V  
12Ω  
-0.75A  
-2.4V  
TP0620N3-G P002  
TP0620N3-G P003  
Pin Configuration  
TP0620N3-G P005 3-Lead TO-92  
TP0620N3-G P013  
2000/Reel  
DRAIN  
TP0620N3-G P014  
SOURCE  
-G denotes a lead (Pb)-free / RoHS compliant package.  
Contact factory for Wafer / Die availablity.  
Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant.  
GATE  
TO-92  
Absolute Maximum Ratings  
Parameter  
Value  
BVDSS  
BVDGS  
±20V  
Product Marking  
Drain-to-source voltage  
Drain-to-gate voltage  
SiTP  
0 6 2 0  
YYWW  
YY = Year Sealed  
WW = Week Sealed  
Gate-to-source voltage  
= “Green” Packaging  
Operating and storage temperature  
-55OC to +150OC  
Package may or may not include the following marks: Si or  
Absolute Maximum Ratings are those values beyond which damage to the device  
may occur. Functional operation under these conditions is not implied. Continuous  
operation of the device at the absolute rating level may affect device reliability. All  
voltages are referenced to device ground.  
TO-92  
Typical Thermal Resistance  
Package  
θja  
TO-92  
132OC/W  
Doc.# DSFP-TP0620  
C081313  
Supertex inc.  
www.supertex.com  
12345

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