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TMS570LS3135 PDF预览

TMS570LS3135

更新时间: 2024-10-28 11:58:23
品牌 Logo 应用领域
德州仪器 - TI 闪存微控制器
页数 文件大小 规格书
154页 2867K
描述
TMS570LSxxx5 16/32-Bit RISC Flash Microcontroller

TMS570LS3135 数据手册

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TMS570LS2125  
TMS570LS2135  
TMS570LS3135  
www.ti.com  
SPNS164SEPTEMBER 2011  
TMS570LSxxx5 16/32-Bit RISC Flash Microcontroller  
Check for Samples: TMS570LS2125  
1 TMS570LSxxx5 16/32-Bit RISC Flash Microcontroller  
1.1 Features  
1
High-Performance Automotive Grade  
Multiple Communication Interfaces  
FlexRay Controller with 2 channels  
Microcontroller for Safety Critical Applications  
Dual CPUs running in lockstep  
ECC on flash and RAM interfaces  
8KB message RAM with parity protection  
Dedicated Transfer Unit (FTU)  
Built-In Self Test for CPU and on-chip RAMs  
Error Signaling Module with Error Pin  
Voltage and Clock Monitoring  
Three CAN Controllers (DCAN)  
64 mailboxes with parity protection each  
Compliant to CAN protocol version 2.0B  
Inter-Integrated Circuit (I2C)  
ARM® Cortex™ – R4F 32-bit RISC CPU  
Efficient 1.6DMIPS/MHz with 8-stage pipeline  
Three Multi-buffered Serial Peripheral  
Floating-Point Unit with Single/Double  
Interfaces (MibSPI)  
Precision  
128 Words with Parity Protection each  
12-Region Memory Protection Unit  
Open Architecture with 3rd Party Support  
Operating Conditions  
Two Standard Serial Peripheral Interfaces  
(SPI)  
Local Interconnect Network Interface (LIN)  
Controller  
Up to 180MHz System Clock  
Compliant to LIN protocol version 2.1  
Core Supply Voltage (VCC): 1.2V nominal  
I/O Supply Voltage (VCCIO): 3.3V nominal  
Integrated Memory  
Up to 3MB Program Flash with ECC  
Up to 256KB RAM with ECC  
64KB Flash for emulated EEPROM  
16- bit External Memory Interface  
Common Platform Architecture  
Consistent memory map across family  
Real-Time Interrupt Timer (RTI) OS Timer  
96-channel Vectored Interrupt Module (VIM)  
2-channel Cyclic Redundancy Checker (CRC)  
Direct Memory Access (DMA) Controller  
16 Channels and 32 Control Packets  
Parity protection for control packet RAM  
DMA Accesses Protected by Dedicated MPU  
Standard Serial Communication Interface  
(SCI)  
Two High-End Timer Modules (N2HET)  
N2HET1: 32 programmable channels  
N2HET2: 20 programmable channels  
160 Word Instruction RAM with parity  
protection each  
Each includes Hardware Angle Generator  
Dedicated Transfer Unit for each N2HET  
(HTU)  
Two 10/12-bit Multi-Buffered ADC Modules  
ADC1: 24 channels  
ADC2: 16 channels  
16 shared channels  
64 result buffers with parity protection each  
Packages  
Frequency-Modulated Phase-Locked-Loop  
(FMPLL) with Built-In Slip Detector  
Separate Non-Modulating PLL for FlexRay  
144-pin Quad Flatpack (PGE) [Green]  
337-Ball Grid Array (ZWT) [Green]  
IEEE 1149.1 JTAG, Boundary Scan and ARM  
CoreSight Components  
JTAG Security Module  
Trace and Calibration Capabilities  
Embedded Trace Macrocell (ETM-R4)  
Data Modification Module (DMM)  
RAM Trace Port (RTP)  
Parameter Overlay Module (POM)  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCT PREVIEW information concerns products in the formative  
Copyright © 2011, Texas Instruments Incorporated  
or design phase of development. Characteristic data and other  
specifications are design goals. Texas Instruments reserves the right  
to change or discontinue these products without notice.  
 
 

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