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TMS320C6701GJC120 PDF预览

TMS320C6701GJC120

更新时间: 2024-10-26 14:45:15
品牌 Logo 应用领域
德州仪器 - TI 时钟外围集成电路
页数 文件大小 规格书
71页 961K
描述
32-BIT, 120MHz, OTHER DSP, PBGA352, PLASTIC, BGA-352

TMS320C6701GJC120 技术参数

生命周期:Obsolete零件包装代码:BGA
包装说明:HBGA,针数:352
Reach Compliance Code:unknownECCN代码:3A001.A.3
HTS代码:8542.31.00.01风险等级:5.68
地址总线宽度:32桶式移位器:NO
边界扫描:YES最大时钟频率:120 MHz
外部数据总线宽度:32格式:FLOATING POINT
内部总线架构:MULTIPLEJESD-30 代码:S-PBGA-B352
长度:35 mm低功率模式:YES
端子数量:352封装主体材料:PLASTIC/EPOXY
封装代码:HBGA封装形状:SQUARE
封装形式:GRID ARRAY, HEAT SINK/SLUG认证状态:Not Qualified
座面最大高度:3.5 mm最大供电电压:3.46 V
最小供电电压:3.14 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
端子形式:BALL端子节距:1.27 mm
端子位置:BOTTOM宽度:35 mm
uPs/uCs/外围集成电路类型:DIGITAL SIGNAL PROCESSOR, OTHERBase Number Matches:1

TMS320C6701GJC120 数据手册

 浏览型号TMS320C6701GJC120的Datasheet PDF文件第2页浏览型号TMS320C6701GJC120的Datasheet PDF文件第3页浏览型号TMS320C6701GJC120的Datasheet PDF文件第4页浏览型号TMS320C6701GJC120的Datasheet PDF文件第5页浏览型号TMS320C6701GJC120的Datasheet PDF文件第6页浏览型号TMS320C6701GJC120的Datasheet PDF文件第7页 
ꢀ ꢁꢂꢃ ꢄꢅ ꢆꢇ ꢈꢅ ꢉ  
ꢀꢍ  
SPRS067F − MAY 1998 − REVISED MARCH 2004  
D
D
Highest Performance Floating-Point Digital  
Signal Processor (DSP) TMS320C6701  
− 8.3-, 6.7-, 6-ns Instruction Cycle Time  
− 120-, 150-, 167-MHz Clock Rate  
− Eight 32-Bit Instructions/Cycle  
− 1 GFLOPS  
GJC (352-PIN BGA) PACKAGE  
(BOTTOM VIEW)  
26  
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
− TMS320C6201 Fixed-Point DSP  
Pin-Compatible  
VelociTIAdvanced Very Long Instruction  
Word (VLIW) C67x CPU Core  
− Eight Highly Independent Functional  
Units:  
R
T
U
V
W
Y
AA  
AB  
AC  
AD  
AE  
AF  
− Four ALUs (Floating- and Fixed-Point)  
− Two ALUs (Fixed-Point)  
− Two Multipliers (Floating- and  
Fixed-Point)  
− Load-Store Architecture With 32 32-Bit  
General-Purpose Registers  
− Instruction Packing Reduces Code Size  
− All Instructions Conditional  
D
Instruction Set Features  
− Hardware Support for IEEE  
Single-Precision Instructions  
− Hardware Support for IEEE  
Double-Precision Instructions  
− Byte-Addressable (8-, 16-, 32-Bit Data)  
− 8-Bit Overflow Protection  
− Saturation  
D
16-Bit Host-Port Interface (HPI)  
− Access to Entire Memory Map  
D
Two Multichannel Buffered Serial Ports  
(McBSPs)  
− Direct Interface to T1/E1, MVIP, SCSA  
Framers  
− Bit-Field Extract, Set, Clear  
− Bit-Counting  
− Normalization  
− ST-Bus-Switching Compatible  
− Up to 256 Channels Each  
− AC97-Compatible  
− Serial-Peripheral-Interface (SPI)  
Compatible (Motorola)  
D
D
1M-Bit On-Chip SRAM  
− 512K-Bit Internal Program/Cache  
(16K 32-Bit Instructions)  
− 512K-Bit Dual-Access Internal Data  
(64K Bytes)  
D
D
D
D
D
Two 32-Bit General-Purpose Timers  
Flexible Phase-Locked-Loop (PLL) Clock  
Generator  
32-Bit External Memory Interface (EMIF)  
− Glueless Interface to Synchronous  
Memories: SDRAM and SBSRAM  
− Glueless Interface to Asynchronous  
Memories: SRAM and EPROM  
− 52M-Byte Addressable External Memory  
Space  
IEEE-1149.1 (JTAG )  
Boundary-Scan-Compatible  
352-Pin Ball Grid Array (BGA) Package  
(GJC Suffix)  
0.18-µm/5-Level Metal Process  
− CMOS Technology  
D
Four-Channel Bootloading  
Direct-Memory-Access (DMA) Controller  
With an Auxiliary Channel  
D
3.3-V I/Os, 1.8-V Internal (120-, 150-MHz)  
3.3-V I/Os, 1.9-V Internal (167-MHz Only)  
D
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
VelociTI is a trademark of Texas Instruments.  
Motorola is a trademark of Motorola, Inc.  
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.  
ꢀꢢ  
Copyright 2004, Texas Instruments Incorporated  
ꢞ ꢢ ꢟ ꢞꢗ ꢘꢬ ꢚꢙ ꢝ ꢥꢥ ꢣꢝ ꢛ ꢝ ꢜ ꢢ ꢞ ꢢ ꢛ ꢟ ꢧ  
1
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443  

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