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TMS320C6711CGDP200 PDF预览

TMS320C6711CGDP200

更新时间： 2024-11-17 22:09:35
品牌 Logo 应用领域
德州仪器 - TI 微控制器和处理器外围集成电路数字信号处理器时钟
页数 文件大小 规格书
129页 1914K
描述
FLOATING-POINT DIGITAL SIGNAL PROCESSORS

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TMS320C6711CGDP200 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Obsolete零件包装代码：BGA
包装说明：BGA, BGA272,20X20,50针数：272
Reach Compliance Code：not_compliantECCN代码：3A001.A.3
HTS代码：8542.31.00.01Factory Lead Time：1 week
风险等级：5.8Is Samacsys：N
其他特性：ALSO REQUIRES 3.3V SUPPLY地址总线宽度：22
桶式移位器：NO位大小：32
边界扫描：YES最大时钟频率：200 MHz
外部数据总线宽度：32格式：FLOATING POINT
内部总线架构：MULTIPLEJESD-30 代码：S-PBGA-B272
长度：27 mm低功率模式：YES
端子数量：272封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装等效代码：BGA272,20X20,50
封装形状：SQUARE封装形式：GRID ARRAY
峰值回流温度（摄氏度）：NOT SPECIFIED电源：1.2,3.3 V
认证状态：Not QualifiedRAM（字数）：65536
座面最大高度：2.57 mm子类别：Digital Signal Processors
最大供电电压：1.32 V最小供电电压：1.14 V
标称供电电压：1.2 V表面贴装：YES
技术：CMOS端子形式：BALL
端子节距：1.27 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：27 mm
uPs/uCs/外围集成电路类型：DIGITAL SIGNAL PROCESSOR, OTHERBase Number Matches：1

TMS320C6711CGDP200 数据手册

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TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D  
FLOATING-POINT DIGITAL SIGNAL PROCESSORS  
SPRS088L − FEBRUARY 1999 − REVISED MAY 2004  
D
D
Excellent-Price/Performance Floating-Point  
Digital Signal Processors (DSPs):  
TMS320C67x(C6711, C6711B, C6711C,  
and C6711D)  
− Eight 32-Bit Instructions/Cycle  
− 100-,150-,167-,200-,250-MHz Clock Rates  
− 10-, 6.7-, 6-, 5-, 4-ns Instruction Cycle  
Time  
D
32-Bit External Memory Interface (EMIF)  
− Glueless Interface to Asynchronous  
Memories: SRAM and EPROM  
− Glueless Interface to Synchronous  
Memories: SDRAM and SBSRAM  
− 256M-Byte Total Addressable External  
Memory Space  
D
D
16-Bit Host-Port Interface (HPI)  
− 600, 900, 1000, 1200, 1500 MFLOPS  
Two Multichannel Buffered Serial Ports  
(McBSPs)  
− Direct Interface to T1/E1, MVIP, SCSA  
Framers  
− ST-Bus-Switching Compatible  
− Up to 256 Channels Each  
− AC97-Compatible  
− Serial-Peripheral-Interface (SPI)  
Compatible (Motorola)  
Advanced Very Long Instruction Word  
(VLIW) C67xDSP Core  
− Eight Highly Independent Functional  
Units:  
− Four ALUs (Floating- and Fixed-Point)  
− Two ALUs (Fixed-Point)  
− Two Multipliers (Floating- and  
Fixed-Point)  
− Load-Store Architecture With 32 32-Bit  
General-Purpose Registers  
− Instruction Packing Reduces Code Size  
− All Instructions Conditional  
D
D
Two 32-Bit General-Purpose Timers  
Flexible Phase-Locked-Loop (PLL) Clock  
Generator [C6711/11B]  
D
D
D
D
D
D
Flexible Software Configurable PLL-Based  
Clock Generator Module [C6711C/11D]  
D
D
Instruction Set Features  
− Hardware Support for IEEE  
Single-Precision and Double-Precision  
Instructions  
− Byte-Addressable (8-, 16-, 32-Bit Data)  
− 8-Bit Overflow Protection  
− Saturation  
− Bit-Field Extract, Set, Clear  
− Bit-Counting  
− Normalization  
A Dedicated General-Purpose Input/Output  
(GPIO) Module With 5 Pins [C6711C/11D]  
†
IEEE-1149.1 (JTAG )  
Boundary-Scan-Compatible  
256-Pin Ball Grid Array (BGA) Package  
(GFN Suffix) [C6711/C6711B Only]  
272-Pin Ball Grid Array (BGA) Package  
(GDP Suffix) [C6711C/C6711D Only]  
L1/L2 Memory Architecture  
− 32K-Bit (4K-Byte) L1P Program Cache  
(Direct Mapped)  
− 32K-Bit (4K-Byte) L1D Data Cache  
(2-Way Set-Associative)  
− 512K-Bit (64K-Byte) L2 Unified Mapped  
RAM/Cache  
CMOS Technology  
− 0.13-µm/6-Level Copper Metal Process  
(C6711C/C6711D)  
− 0.18-µm/5-Level Copper Metal Process  
(C6711/11B)  
D
D
D
D
3.3-V I/O, 1.4-V Internal (C6711D−250)  
3.3-V I/O, 1.20-V Internal (C6711C/C6711D)‡  
3.3-V I/O, 1.8-V Internal (C6711B/C6711−100)  
3.3-V I/O, 1.9-V Internal (C6711-150)  
(Flexible Data/Program Allocation)  
D
D
Device Configuration  
− Boot Mode: HPI, 8-, 16-, 32-Bit ROM Boot  
− Endianness: Little Endian, Big Endian  
Enhanced Direct-Memory-Access (EDMA)  
Controller (16 Independent Channels)  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
TMS320C67x and C67x are trademarks of Texas Instruments.  
Motorola is a trademark of Motorola, Inc.  
All trademarks are the property of their respective owners.  
†
‡
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.  
These values are compatible with existing 1.26V designs.  
This document contains information on products in more than one phase  
of development. The status of each device is indicated on the page(s)  
specifying its electrical characteristics.  
Copyright 2004, Texas Instruments Incorporated  
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
1234567...129

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