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TMS320C6711BGFNA100 PDF预览

TMS320C6711BGFNA100

更新时间: 2024-11-15 23:36:27
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85页 1193K
描述
DSP|32-BIT|CMOS|BGA|256PIN|PLASTIC

TMS320C6711BGFNA100 数据手册

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TMS320C6711, TMS320C6711B  
FLOATING-POINT DIGITAL SIGNAL PROCESSORS  
SPRS088B – FEBRUARY 1999 – REVISED SEPTEMBER 2001  
D
D
Excellent Price/Performance Digital Signal  
Processors (DSPs): TMS320C67x  
(TMS320C6711 and TMS320C6711B)  
– Eight 32-Bit Instructions/Cycle  
– C6211, C6211B, C6711, and C6711B are  
Pin-Compatible  
– 100-, 150-MHz Clock Rates  
– 10-, 6.7-ns Instruction Cycle Time  
– 600, 900 MFLOPS  
D
D
Device Configuration  
– Boot Mode: HPI, 8-, 16-, and 32-Bit ROM  
Boot  
– Endianness: Little Endian, Big Endian  
32-Bit External Memory Interface (EMIF)  
– Glueless Interface to Asynchronous  
Memories: SRAM and EPROM  
– Glueless Interface to Synchronous  
Memories: SDRAM and SBSRAM  
– 512M-Byte Total Addressable External  
Memory Space  
VelociTI Advanced Very Long Instruction  
Word (VLIW) C67x DSP Core (C6711/11B)  
– Eight Highly Independent Functional  
Units:  
D
D
D
Enhanced Direct-Memory-Access (EDMA)  
Controller (16 Independent Channels)  
– Four ALUs (Floating- and Fixed-Point)  
– Two ALUs (Fixed-Point)  
– Two Multipliers (Floating- and  
Fixed-Point)  
16-Bit Host-Port Interface (HPI)  
– Access to Entire Memory Map  
Two Multichannel Buffered Serial Ports  
(McBSPs)  
– Direct Interface to T1/E1, MVIP, SCSA  
Framers  
– ST-Bus-Switching Compatible  
– Up to 256 Channels Each  
– AC97-Compatible  
– Serial-Peripheral-Interface (SPI)  
Compatible (Motorola )  
– Load-Store Architecture With 32 32-Bit  
General-Purpose Registers  
– Instruction Packing Reduces Code Size  
– All Instructions Conditional  
D
D
Instruction Set Features  
– Hardware Support for IEEE  
Single-Precision and Double-Precision  
Instructions  
– Byte-Addressable (8-, 16-, 32-Bit Data)  
– 8-Bit Overflow Protection  
– Saturation  
– Bit-Field Extract, Set, Clear  
– Bit-Counting  
– Normalization  
D
D
Two 32-Bit General-Purpose Timers  
Flexible Phase-Locked-Loop (PLL) Clock  
Generator  
D
D
D
D
IEEE-1149.1 (JTAG )  
Boundary-Scan-Compatible  
256-Pin Ball Grid Array (BGA) Package  
(GFN Suffix)  
L1/L2 Memory Architecture  
– 32K-Bit (4K-Byte) L1P Program Cache  
(Direct Mapped)  
– 32K-Bit (4K-Byte) L1D Data Cache  
(2-Way Set-Associative)  
0.18-µm/5-Level Metal Process  
– CMOS Technology  
3.3-V I/Os, 1.8-V Internal  
– 512K-Bit (64K-Byte) L2 Unified Mapped  
RAM/Cache  
(Flexible Data/Program Allocation)  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
TMS320C67x, VelociTI, and C67x are trademarks of Texas Instruments.  
Motorola is a trademark of Motorola, Inc.  
All trademarks are the property of their respective owners.  
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.  
Copyright 2001, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443  

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C67x 浮点 DSP- 高达 250MHz、McBSP、32 位 EMIFA | ZDP