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TMS320C6701GJL100 PDF预览

TMS320C6701GJL100

更新时间: 2024-11-18 05:24:27
品牌 Logo 应用领域
德州仪器 - TI 数字信号处理器
页数 文件大小 规格书
70页 1074K
描述
FIXED-POINT DIGITAL SIGNAL PROCESSOR

TMS320C6701GJL100 数据手册

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TMS320C6205  
FIXED-POINT DIGITAL SIGNAL PROCESSOR  
SPRS106E OCTOBER 1999 REVISED MARCH 2004  
D
D
High-Performance Fixed-Point Digital  
Signal Processor (DSP) TMS320C6205  
5-ns Instruction Cycle Time  
200-MHz Clock Rate  
Eight 32-Bit Instructions/Cycle  
1600 MIPS  
D
32-Bit/33-MHz  
Interconnect (PCI) Master/Slave Interface  
Conforms to:  
Peripheral  
Component  
PCI Specification 2.2  
Power Management Interface 1.1  
Meets Requirements of PC99  
PCI Access to All On-Chip RAM,  
Peripherals, and External Memory  
(via EMIF)  
Four 8-Deep x 32-Wide FIFOs for  
Efficient PCI Bus Data Transfer  
3.3/5-V PCI Operation  
Three PCI Bus Address Registers:  
Prefetchable Memory  
Non-Prefetchable Memory I/O  
Supports 4-Wire Serial EEPROM  
Interface  
VelociTIAdvanced-Very-Long-Instruction-  
Word (VLIW) TMS320C62xDSP Core  
Eight Highly Independent Functional  
Units:  
Six ALUs (32-/40-Bit)  
Two 16-Bit Multipliers (32-Bit Result)  
Load-Store Architecture With 32 32-Bit  
General-Purpose Registers  
Instruction Packing Reduces Code Size  
All Instructions Conditional  
D
D
D
Instruction Set Features  
Byte-Addressable (8-, 16-, 32-Bit Data)  
8-Bit Overflow Protection  
Saturation  
Bit-Field Extract, Set, Clear  
Bit-Counting  
PCI Interrupt Request Under DSP  
Program Control  
DSP Interrupt Via PCI I/O Cycle  
D
Two Multichannel Buffered Serial Ports  
(McBSPs)  
Direct Interface to T1/E1, MVIP, SCSA  
Framers  
ST-Bus-Switching Compatible  
Up to 256 Channels Each  
AC97-Compatible  
Serial-Peripheral-Interface (SPI)  
Compatible (Motorola)  
Normalization  
1M-Bit On-Chip SRAM  
512K-Bit Internal Program/Cache  
(16K 32-Bit Instructions)  
512K-Bit Dual-Access Internal Data  
(64K Bytes)  
Organized as Two 32K-Byte Blocks for  
Improved Concurrency  
D
D
D
D
D
Two 32-Bit General-Purpose Timers  
IEEE-1149.1 (JTAG )  
Boundary-Scan-Compatible  
32-Bit External Memory Interface (EMIF)  
Glueless Interface to Synchronous  
Memories: SDRAM or SBSRAM  
Glueless Interface to Asynchronous  
Memories: SRAM and EPROM  
52M-Byte Addressable External Memory  
Space  
288-Pin MicroStar BGAPackage  
(GHK Suffix)  
0.15-µm/5-Level Metal Process  
CMOS Technology  
3.3-V I/Os, 1.5-V Internal, 5-V Voltage  
Tolerance for PCI I/O Pins  
D
D
Four-Channel Bootloading  
Direct-Memory-Access (DMA) Controller  
With an Auxiliary Channel  
Flexible Phase-Locked-Loop (PLL) Clock  
Generator  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
VelociTI, TMS320C62x, and MicroStar BGA are trademarks of Texas Instruments.  
Motorola is a trademark of Motorola, Inc.  
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.  
Copyright 2004, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 1443 HOUSTON, TEXAS 772511443  

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