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TMS320C6711D_07

更新时间： 2024-11-16 05:29:11
品牌 Logo 应用领域
德州仪器 - TI 数字信号处理器
页数 文件大小 规格书
108页 1435K
描述
FLOATING-POINT DIGITAL SIGNAL PROCESSOR

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TMS320C6711D_07 数据手册

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SPRS292B − OCTOBER 2005 − REVISED JUNE 2006  
D
D
Excellent-Price/Performance Floating-Point  
Digital Signal Processor (DSP):  
TMS320C6711D  
− Eight 32-Bit Instructions/Cycle  
− 167-, 200-, 250-MHz Clock Rates  
− 6-, 5-, 4-ns Instruction Cycle Time  
− 1000, 1200, 1500 MFLOPS  
D
32-Bit External Memory Interface (EMIF)  
− Glueless Interface to Asynchronous  
Memories: SRAM and EPROM  
− Glueless Interface to Synchronous  
Memories: SDRAM and SBSRAM  
− 256M-Byte Total Addressable External  
Memory Space  
Advanced Very Long Instruction Word  
(VLIW) C67xDSP Core  
− Eight Highly Independent Functional  
Units:  
D
D
16-Bit Host-Port Interface (HPI)  
Two Multichannel Buffered Serial Ports  
(McBSPs)  
− Direct Interface to T1/E1, MVIP, SCSA  
Framers  
− ST-Bus-Switching Compatible  
− Up to 256 Channels Each  
− AC97-Compatible  
− Four ALUs (Floating- and Fixed-Point)  
− Two ALUs (Fixed-Point)  
− Two Multipliers (Floating- and  
Fixed-Point)  
− Load-Store Architecture With 32 32-Bit  
General-Purpose Registers  
− Instruction Packing Reduces Code Size  
− All Instructions Conditional  
− Serial-Peripheral-Interface (SPI)  
Compatible (Motorola)  
Two 32-Bit General-Purpose Timers  
D
D
Flexible Software Configurable PLL-Based  
Clock Generator Module  
D
D
Instruction Set Features  
− Hardware Support for IEEE  
Single-Precision and Double-Precision  
Instructions  
− Byte-Addressable (8-, 16-, 32-Bit Data)  
− 8-Bit Overflow Protection  
− Saturation  
− Bit-Field Extract, Set, Clear  
− Bit-Counting  
− Normalization  
D
D
D
D
A Dedicated General-Purpose Input/Output  
(GPIO) Module With 5 Pins  
†
IEEE-1149.1 (JTAG )  
Boundary-Scan-Compatible  
272-Pin Ball Grid Array (BGA) Package  
(GDP and ZDP Suffixes)  
CMOS Technology  
− 0.13-µm/6-Level Copper Metal Process  
3.3-V I/O, 1.4-V Internal (−250)  
L1/L2 Memory Architecture  
− 32K-Bit (4K-Byte) L1P Program Cache  
(Direct Mapped)  
− 32K-Bit (4K-Byte) L1D Data Cache  
(2-Way Set-Associative)  
D
‡
D
3.3-V I/O, 1.20-V Internal  
− 512K-Bit (64K-Byte) L2 Unified Mapped  
RAM/Cache  
(Flexible Data/Program Allocation)  
D
D
Device Configuration  
− Boot Mode: HPI, 8-, 16-, 32-Bit ROM Boot  
− Endianness: Little Endian, Big Endian  
Enhanced Direct-Memory-Access (EDMA)  
Controller (16 Independent Channels)  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
TMS320C67x and C67x are trademarks of Texas Instruments.  
Motorola is a trademark of Motorola, Inc.  
All trademarks are the property of their respective owners.  
†
‡
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.  
These values are compatible with existing 1.26V designs.  
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Copyright 2006, Texas Instruments Incorporated  
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1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
1234567...108

中文翻译

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