TMS320C6711, TMS320C6711B, TMS320C6711C
FLOATING-POINT DIGITAL SIGNAL PROCESSORS
SPRS088H − FEBRUARY 1999 − REVISED JULY 2003
D Excellent Price/Performance Digital Signal
Processors (DSPs): TMS320C67x
(TMS320C6711, C6711B, and C6711C)
− Eight 32-Bit Instructions/Cycle
D 32-Bit External Memory Interface (EMIF)
− Glueless Interface to Asynchronous
Memories: SRAM and EPROM
− Glueless Interface to Synchronous
Memories: SDRAM and SBSRAM
− 256M-Byte Total Addressable External
Memory Space
− 100-, 150-, 167-, 200-MHz Clock Rates
− 10-, 6.7-, 6-, 5-ns Instruction Cycle Time
− 600, 900, 1000, 1200 MFLOPS
D VelociTI Advanced Very Long Instruction
Word (VLIW) C67x DSP Core
− Eight Highly Independent Functional
Units:
D 16-Bit Host-Port Interface (HPI)
D Two Multichannel Buffered Serial Ports
(McBSPs)
− Direct Interface to T1/E1, MVIP, SCSA
Framers
− ST-Bus-Switching Compatible
− Up to 256 Channels Each
− AC97-Compatible
− Serial-Peripheral-Interface (SPI)
Compatible (Motorola)
− Four ALUs (Floating- and Fixed-Point)
− Two ALUs (Fixed-Point)
− Two Multipliers (Floating- and
Fixed-Point)
− Load-Store Architecture With 32 32-Bit
General-Purpose Registers
− Instruction Packing Reduces Code Size
D Two 32-Bit General-Purpose Timers
− All Instructions Conditional
D Flexible Phase-Locked-Loop (PLL) Clock
D Instruction Set Features
− Hardware Support for IEEE
Single-Precision and Double-Precision
Instructions
Generator [C6711/11B]
D Flexible Software Configurable PLL-Based
Clock Generator Module [C6711C]
− Byte-Addressable (8-, 16-, 32-Bit Data)
− 8-Bit Overflow Protection
− Saturation
− Bit-Field Extract, Set, Clear
− Bit-Counting
D A Dedicated General-Purpose Input/Output
(GPIO) Module With 5 Pins [C6711C]
†
D IEEE-1149.1 (JTAG )
Boundary-Scan-Compatible
D 256-Pin Ball Grid Array (BGA) Package
− Normalization
(GFN Suffix) [C6711/C6711B Only]
D L1/L2 Memory Architecture
− 32K-Bit (4K-Byte) L1P Program Cache
(Direct Mapped)
D 272-Pin Ball Grid Array (BGA) Package
(GDP Suffix) [C6711C Only]
D CMOS Technology
− 32K-Bit (4K-Byte) L1D Data Cache
(2-Way Set-Associative)
− 512K-Bit (64K-Byte) L2 Unified Mapped
− 0.13-µm/6-Level Copper Metal Process
(C6711C)
− 0.18-µm/5-Level Copper Metal Process
RAM/Cache
(Flexible Data/Program Allocation)
(C6711/11B)
D 3.3-V I/O, 1.26-V Internal (C6711C)
D Device Configuration
D 3.3-V I/O, 1.8-V Internal (C6711B/C6711−100)
D 3.3-V I/O, 1.9-V Internal (C6711-150)
− Boot Mode: HPI, 8-, 16-, and 32-Bit ROM
Boot
− Endianness: Little Endian, Big Endian
D Enhanced Direct-Memory-Access (EDMA)
Controller (16 Independent Channels)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TMS320C67x, VelociTI, and C67x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
All trademarks are the property of their respective owners.
†
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
Copyright 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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