SY100S811ZHTR

更新时间： 2024-11-06 05:04:27

品牌	Logo	应用领域
麦瑞 - MICREL		/
页数	文件大小	规格书
6页	101K
描述
SINGLE SUPPLY 1:9 PECL/TTL-TO-PECL

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SY100S811ZHTR 数据手册

Precision Edge^®

Precision^SE^Yd¹g⁰⁰e^S811

Micrel, Inc.

SINGLE SUPPLY 1:9

PECL/TTL-TO-PECL

SY100S811

FEATURES

■ PECL version of popular ECLinPS E111

■ Low skew

Precision Edge

■ Guaranteed skew spec

DESCRIPTION

■ VBB output

■ TTL enable input

The SY100S811 is a low skew 1-to-9 PECL differential

driver designed for clock distribution in new, high-

performance PECL systems. It accepts either a PECL

clock input or a TTL input by using the TTL enable pin TEN.

When the TTL enable pin is HIGH, the TTL input is enabled

and the PECL input is disabled. When the enable pin is set

LOW, the TTL input is disabled and the PECL input is

enabled.

The device is specifically designed and produced for low

skew. The interconnect scheme and metal layout are

carefully optimized for minimal gate-to-gate skew within

the device. Wafer characterization and process control

ensure consistent distribution of propagation delay from lot

to lot. Since the S811 shares a common set of “basic”

processing with the other members of the ECLinPS family,

wafer characterization at the point of device personalization

allows for tighter control of parameters, including

propagation delay.

■ Selectable TTL or PECL clock input

■ Single +5V supply

■ Differential internal design

■ Similar pin configuration to E111

■ PECL I/O fully compatible with industry standard

■ Internal 75KΩ PECL input pull-down resistors

■ Available in 28-pin PLCC and SOIC packages

BLOCK DIAGRAM

To ensure that the skew specification is met, it is

necessary that both sides of the differential output are

terminated into 50Ω, even if only one side is being used. ln

most applications, all nine differential pairs will be used

and, therefore, terminated. In the case where fewer than

nine pairs are used, it is necessary to terminate at least the

output pairs on the same package side (i.e. sharing the

same VCCO as the pair(s) being used on that side) in order

to maintain minimum skew.

The VBB output is intended for use as a reference

voltage for single-ended reception of PECL signals to that

device only. When using VBB for this purpose, it is

recommended that VBB is decoupled to VCC via a 0.01µF

capacitor.

Precision Edge is a registered trademark of Micrel, Inc.

Rev.: H

Amendment: /0

M9999-021407

hbwhelp@micrel.com or (408) 955-1690

Issue Date: February 2007

12 3 4 5 6

中文翻译

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与SY100S811ZHTR相关器件

型号	品牌	获取价格	描述	数据表
SY100S815	MICREL	获取价格	SINGLE SUPPLY QUAD PECL/TTL-TO-PECL
SY100S815_06	MICREL	获取价格	SINGLE SUPPLY QUAD PECL/TTL-TO-PECL
SY100S815ZC	MICREL	获取价格	SINGLE SUPPLY QUAD PECL/TTL-TO-PECL
SY100S815ZCTR	MICREL	获取价格	SINGLE SUPPLY QUAD PECL/TTL-TO-PECL
SY100S815ZG	MICREL	获取价格	SINGLE SUPPLY QUAD PECL/TTL-TO-PECL
SY100S815ZGTR	MICREL	获取价格	SINGLE SUPPLY QUAD PECL/TTL-TO-PECL
SY100S815ZG-TR	MICROCHIP	获取价格	100S SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
SY100S815ZH	MICROCHIP	获取价格	100S SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
SY100S834	MICREL	获取价格	(±1, ±2, ±4) OR (±2, ±4, ±8) CLOCK GENERATION
SY100S834/L	ETC	获取价格	(÷1. ÷2. ÷4) or (÷2. ÷4. ÷8) PECL Clock Gener

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