SY100S815

更新时间： 2024-11-05 22:59:23

品牌	Logo	应用领域
麦瑞 - MICREL		/
页数	文件大小	规格书
4页	70K
描述
SINGLE SUPPLY QUAD PECL/TTL-TO-PECL

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中文翻译

获取价格

数据手册

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SY100S815 数据手册

SINGLE SUPPLY QUAD

PECL/TTL-TO-PECL

ClockWorks™

SY100S815

FEATURES

DESCRIPTION

The SY100S815 is a low skew 1-to-4 PECL differential

driver designed for clock distribution in new, high-

performance PECL systems. It accepts either a PECL

clock input or a TTL input by using the TTL enable pin TEN.

When the TTL enable pin is HIGH, the TTL input is enabled

and the PECL input is disabled. When the enable pin is set

LOW, the TTL input is disabled and the PECL input is

enabled.

The device is specifically designed and produced for low

skew. The interconnect scheme and metal layout are

carefully optimized for minimal gate-to-gate skew within

the device. Wafer characterization and process control

ensure consistent distribution of propagation delay from lot

to lot. Since the S815 shares a common set of “basic”

processing with the other members of the ECLinPS family,

wafer characterization at the point of device personalization

allows for tighter control of parameters, including

propagation delay.

To ensure that the skew specification is met, it is

necessary that both sides of the differential output are

terminated into 50Ω, even if only one side is being used. In

most applications, all nine differential pairs will be used

and, therefore, terminated. In the case where fewer than

nine pairs are used, it is necessary to terminate at least the

output pairs on the same package side (i.e. sharing the

same VCCO as the pair(s) being used on that side) in order

to maintain minimum skew.

■ Quad PECL version of popular ECLinPS E111

■ Low skew

■ Guaranteed skew spec

■ TTL enable input

■ Selectable TTL or PECL clock input

■ Single +5V supply

■ Differential internal design

■ PECL I/O fully compatible with industry standard

■ Internal 75kΩ PECL input pull-down resistors

■ Available in 16-pin SOIC package

BLOCK DIAGRAM

EIN

TIN

PIN CONFIGURATION

TEN

VCC

EIN

TEN

VEE

EIN

TIN

PIN NAMES

TOP VIEW

SOIC

Z16-1

EIN, EIN

TIN

Function

Differential PECL Input Pair

TTL Input

TEN

TTL Input Enable

VCCO

Q0, Q0 – Q3, Q3

Differential PECL Outputs

PECL VCC (+5.0V)

PECL Ground (0V)

VCC

VEE

Rev.: F

Amendment: /0

Issue Date: October, 1998

12 3 4

中文翻译

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与SY100S815相关器件

型号	品牌	获取价格	描述	数据表
SY100S815_06	MICREL	获取价格	SINGLE SUPPLY QUAD PECL/TTL-TO-PECL
SY100S815ZC	MICREL	获取价格	SINGLE SUPPLY QUAD PECL/TTL-TO-PECL
SY100S815ZCTR	MICREL	获取价格	SINGLE SUPPLY QUAD PECL/TTL-TO-PECL
SY100S815ZG	MICREL	获取价格	SINGLE SUPPLY QUAD PECL/TTL-TO-PECL
SY100S815ZGTR	MICREL	获取价格	SINGLE SUPPLY QUAD PECL/TTL-TO-PECL
SY100S815ZG-TR	MICROCHIP	获取价格	100S SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
SY100S815ZH	MICROCHIP	获取价格	100S SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
SY100S834	MICREL	获取价格	(±1, ±2, ±4) OR (±2, ±4, ±8) CLOCK GENERATION
SY100S834/L	ETC	获取价格	(÷1. ÷2. ÷4) or (÷2. ÷4. ÷8) PECL Clock Gener
SY100S834_06	MICREL	获取价格	(±1, ±2, ±4) OR (±2, ±4, ±8) CLOCK GENERATION

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