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SY100E241JZ PDF预览

SY100E241JZ

更新时间: 2024-11-24 05:04:31
品牌 Logo 应用领域
麦瑞 - MICREL 移位寄存器触发器逻辑集成电路
页数 文件大小 规格书
4页 62K
描述
8-BIT SCANNABLE REGISTER

SY100E241JZ 技术参数

生命周期:Obsolete零件包装代码:QLCC
包装说明:QCCJ,针数:28
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.18Is Samacsys:N
计数方向:RIGHT系列:100E
JESD-30 代码:S-PQCC-J28JESD-609代码:e3
长度:11.48 mm逻辑集成电路类型:PARALLEL IN PARALLEL OUT
位数:8功能数量:1
端子数量:28最高工作温度:85 °C
最低工作温度:输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装形状:SQUARE封装形式:CHIP CARRIER
传播延迟(tpd):0.975 ns认证状态:Not Qualified
座面最大高度:4.57 mm表面贴装:YES
技术:ECL温度等级:COMMERCIAL EXTENDED
端子面层:MATTE TIN端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
触发器类型:POSITIVE EDGE宽度:11.48 mm
最小 fmax:700 MHzBase Number Matches:1

SY100E241JZ 数据手册

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8-BIT SCANNABLE  
REGISTER  
SY10E241  
SY100E241  
FEATURES  
DESCRIPTION  
1000ps max. CLK to output  
The SY10/100E241 are 8-bit shiftable registers designed  
for use in new, high-performance ECL systems. Unlike the  
E141, the E241 features internal data feedback organized  
such that the SHIFT control overrides the HOLD, /LOAD  
control. Thus, the normal operations of HOLD and LOAD  
can be toggled with a single control line without the need for  
external gating. This configuration also enables switching  
to scan mode with the single SHIFT control line.  
Extended 100E VEE range of –4.2V to –5.5V  
SHIFT overrides HOLD, /LOAD control  
Asynchronous Master Reset  
Pin-compatible with E141  
Fully compatible with industry standard 10KH,  
100K ECL levels  
The eight inputs D0–D7 accept parallel input data, while  
S-IN accepts serial input data when in shift mode. Data is  
accepted a set-up time before the rising edge of CLK.  
Shifting is also accomplished on the rising clock edge. A  
HIGH on the Master Reset pin (MR) asychronously resets  
all the registers to zero.  
Internal 75Kinput pulldown resistors  
Fully compatible with Motorola MC10E/100E241  
Available in 28-pin PLCC package  
PIN NAMES  
BLOCK DIAGRAM  
Pin  
D0–D7  
S-IN  
Function  
Parallel Data Inputs  
Serial Data Input  
SHIFT Control  
HOLD, /LOAD Control  
Clock  
S-IN  
D
D
Q
R
Q
0
D0  
SEL0  
SEL1  
CLK  
Q
R
Q
1
Q6  
MR  
Master Reset  
Q0–Q7  
VCCO  
Data Outputs  
D1 D6  
VCC to Output  
BITS 1-6  
Q
R
Q7  
D
D7  
SEL1 (HOLD/LOAD)  
SEL  
0
(SHIFT)  
CLK  
MR  
Rev.: F  
Amendment: /0  
M9999-032206  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: December 2005  

SY100E241JZ 替代型号

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