SY100E310JY

更新时间： 2024-11-20 08:57:07

品牌	Logo	应用领域
麦瑞 - MICREL		/
页数	文件大小	规格书
6页	72K
描述
3.3V ECL/PECL 2:8 DIFFERENTIAL FANOUT BUFFER

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SY100E310JY 数据手册

SY100E310L

Micrel, Inc.

3.3V ECL/PECL

2:8 DIFFERENTIAL FANOUT BUFFER

SY100E310L

DESCRIPTION

FEATURES

■ Guaranteed AC performance over temperature and

The SY100E310L is a 3.3V, precision 2:8 ECL/PECL

fanout buffer optimized for precision low-skew clock

distribution. The SY100E310L features fully differential clock

paths to minimize both device and system skew resulting in

skew performance of < 50ps. In addition, the device includes

a 2:1 multiplexer input for redundant switchover applications.

voltage:

• > 800MHz f

(typical)

MAX

• < 50ps within-device skew

■ Low voltage operation:

• LVPECL: +3.3V ±10%

The SY100E310L is optimized for low voltage +3.3V

LVPECL or –3.3V LVECL applications.

• LVECL: –3.3V ±10%

■ Internal 75kΩ pull-down resistors

■ Guaranteed over industrial temperature range:

–40°C to +85°C

Data sheets and support documentation can be found on

Micrel’s web site at www.micrel.com.

■ Pin-for-pin, plug-in replacement for MC100LVE310

■ Available in 28-pin PLCC package

APPLICATIONS

CROSS REFERENCE TABLE

■ Communications clock distribution

■ Redundant clock switchover

Micrel Semiconductor

SY100E310LJI

On Semiconductor

MC100LVE310FN

MC100LVE310FNR2

■ High-end server clock distribution

SY100E310LJITR

FUNCTIONAL BLOCK DIAGRAM

TYPICAL PERFORMANCE

Output Swing

vs. Frequency

/Q0

900

800

700

600

500

400

300

200

100

/Q1

/Q2

CLKA

/CLKA

/Q3

CLKB

/CLKB

/Q4

SEL

CLK FREQUENCY (MHz)

/Q5

/Q6

V_BB

/Q7

Rev.: D

Amendment: /0

M9999-032206

hbwhelp@micrel.com or (408) 955-1690

Issue Date: March 2006

12 3 4 5 6

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