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SY100E256JZTR PDF预览

SY100E256JZTR

更新时间: 2024-11-20 05:04:31
品牌 Logo 应用领域
麦瑞 - MICREL /
页数 文件大小 规格书
4页 63K
描述
3-BIT 4:1 MUX-LATCH

SY100E256JZTR 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:QLCC包装说明:QCCJ,
针数:28Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.49
其他特性:THREE 4:1 MUX FOLLOWED BY LATCH系列:100E
JESD-30 代码:S-PQCC-J28JESD-609代码:e3
长度:11.48 mm逻辑集成电路类型:D LATCH
位数:3功能数量:1
端子数量:28最高工作温度:85 °C
最低工作温度:输出特性:OPEN-EMITTER
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装形状:SQUARE
封装形式:CHIP CARRIER传播延迟(tpd):0.8 ns
认证状态:Not Qualified座面最大高度:4.57 mm
表面贴装:YES技术:ECL
温度等级:COMMERCIAL EXTENDED端子面层:MATTE TIN
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD触发器类型:LOW LEVEL
宽度:11.48 mm

SY100E256JZTR 数据手册

 浏览型号SY100E256JZTR的Datasheet PDF文件第2页浏览型号SY100E256JZTR的Datasheet PDF文件第3页浏览型号SY100E256JZTR的Datasheet PDF文件第4页 
3-BIT 4:1  
SY10E256  
SY100E256  
MUX-LATCH  
DESCRIPTION  
FEATURES  
950ps max. data to output  
The SY10/100E256 offer three 4:1 multiplexers followed  
by latches with differential outputs designed for use in new,  
high-performance ECL systems. Separate Select controls  
are provided for the leading 2:1 mux pairs (see block  
diagram).  
Extended 100E VEE range of –4.2V to –5.5V  
850ps max. latch enable to output  
Separate select controls  
Differential outputs  
When the Latch Enable (LEN) is at a logic LOW, the latch  
istransparentandoutputdataiscontrolledbythemultiplexer  
select controls. A logic HIGH on LEN latches the outputs.  
The Master Reset (MR) overrides all other controls to set  
the Q outputs LOW.  
Fully compatible with industry standard 10KH,  
100K ECL levels  
Internal 75Kinput pulldown resistors  
Fully compatible with Motorola MC10E/100E256  
Available in 28-pin PLCC package  
PIN NAMES  
BLOCK DIAGRAM  
Pin  
Function  
Parallel Data Inputs  
First-stage Select Inputs  
Second-stage Select Input  
Latch Enable  
D
0a  
0b  
D0x–D2x  
D
Q
0
0
D
D
D
0c  
0d  
SEL1A, SEL1B  
SEL2  
E
N
Q
R
R
R
LEN  
D1a  
D1b  
D1c  
D1d  
MR  
Master Reset  
D
Q
1
1
Q0, Q0–Q2, Q2  
VCCO  
Data Outputs  
E
N
Q
VCC to Output  
D2a  
D2b  
D2c  
D2d  
Q
2
2
D
E
N
Q
SEL1A  
SEL1B  
SEL  
2
LEN  
MR  
Rev.: G  
Amendment: /0  
M9999-032206  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: March 2006  

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