SY100E241JCTR

更新时间： 2024-11-19 22:15:11

品牌	Logo	应用领域
麦瑞 - MICREL		/
页数	文件大小	规格书
4页	63K
描述
8-BIT SCANNABLE REGISTER

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数据手册

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SY100E241JCTR 数据手册

8-BIT SCANNABLE

SY10E241

SY100E241

FEATURES

DESCRIPTION

■ 1000ps max. CLK to output

The SY10/100E241 are 8-bit shiftable registers designed

for use in new, high-performance ECL systems. Unlike the

E141, the E241 features internal data feedback organized

such that the SHIFT control overrides the HOLD, /LOAD

control. Thus, the normal operations of HOLD and LOAD

can be toggled with a single control line without the need for

external gating. This configuration also enables switching

to scan mode with the single SHIFT control line.

■ Extended 100E VEE range of –4.2V to –5.5V

■ SHIFT overrides HOLD, /LOAD control

■ Asynchronous Master Reset

■ Pin-compatible with E141

■ Fully compatible with industry standard 10KH,

100K ECL levels

The eight inputs D0–D7 accept parallel input data, while

S-IN accepts serial input data when in shift mode. Data is

accepted a set-up time before the rising edge of CLK.

Shifting is also accomplished on the rising clock edge. A

HIGH on the Master Reset pin (MR) asychronously resets

all the registers to zero.

■ Internal 75KΩ input pulldown resistors

■ Fully compatible with Motorola MC10E/100E241

■ Available in 28-pin PLCC package

PIN CONFIGURATION

BLOCK DIAGRAM

S-IN

25 24 23 22 21 20 19

SEL1

CLK

VEE

S-IN

VCC

VCCO

TOP VIEW

PLCC

J28-1

– Q6

D1 – D6

10 11

BITS 1-6

SEL1 (HOLD/LOAD)

PIN NAMES

SEL

(SHIFT)

CLK

D0–D7

S-IN

Function

Parallel Data Inputs

Serial Data Input

SHIFT Control

HOLD, /LOAD Control

Clock

SEL0

SEL1

CLK

Master Reset

Q0–Q7

VCCO

Data Outputs

VCC to Output

Rev.: C

Amendment: /1

Issue Date: February, 1998

12 3 4

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