Datasheet > SUM110N06-3M4L

SUM110N06-3M4L

更新时间： 2024-09-24 21:54:19

品牌	Logo	应用领域
威世 - VISHAY		/
页数	文件大小	规格书
3页	184K
描述
N-Channel 60-V (D-S) 175C MOSFET

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SUM110N06-3M4L 数据手册

SPICE Device Model SUM110N06-3m4L

Vishay Siliconix

N-Channel 60-V (D-S) 175°C MOSFET

CHARACTERISTICS

• N-Channel Vertical DMOS

• Macro Model (Subcircuit Model)

• Level 3 MOS

• Apply for both Linear and Switching Application

• Accurate over the −55 to 125°C Temperature Range

• Model the Gate Charge, Transient, and Diode Reverse Recovery

Characteristics

DESCRIPTION

The attached spice model describes the typical electrical

characteristics of the n-channel vertical DMOS. The subcircuit

model is extracted and optimized over the −55 to 125°C

temperature ranges under the pulsed 0 to 10V gate drive. The

saturated output impedance is best fit at the gate bias near the

threshold voltage.

A novel gate-to-drain feedback capacitance network is used to

model the gate charge characteristics while avoiding convergence

difficulties of the switched C_gdmodel. All model parameter values

are optimized to provide a best fit to the measured electrical data

and are not intended as an exact physical interpretation of the

device.

SUBCIRCUIT MODEL SCHEMATIC

This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate

data sheet of the same number for guaranteed specification limits.

Document Number: 73060

02-Jul-04

www.vishay.com

12 3

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