STK12C68-M
d
SOFTWARE STORE/RECALL CYCLE
(V = 5.0V ± 10%)
CC
SYMBOLS
STK12C68-40M
STK12C68-45M
STK12C68-55M
UNITS
NO.
PARAMETER
Std.
Alt.
MIN
MAX
MIN
MAX
MIN
MAX
28
29
30
31
32
t
t
t
t
t
t
STORE/RECALL Initiation Cycle Time
Chip Enable to Output Inactive
Address Set-up to Chip Enable
Chip Enable Pulse Width
35
45
55
ns
ns
ns
ns
ns
AVAV
RC
p
85
85
85
ELQZ
t
t
t
0
25
0
0
35
0
0
45
0
AVELN
ELEHN
AE
EP
EA
q,r
Chip Disable to Address Change
EHAXN
Note p: Once the software STORE or RECALL cycle is initiated, it completes automatically, ignoring all inputs.
Note q: Noise on the E pin may trigger multiple read cycles from the same address and abort the address sequence.
Note r: If the Chip Enable Pulse Width is less than t (see READ CYCLE #2) but greater than or equal to t , then the data may not be valid at the end
ELQV
ELEHN
of the low pulse, however the STORE or RECALL will still be initiated.
Note s: W must be HIGH when E is LOW during the address sequence in order to initiate a nonvolatile cycle. G may be either HIGH or LOW throughout.
Addresses #1 through #6 are found in the MODE SELECTION table. Address #6 determines whether the STK12C68-M performs a STORE or RECALL.
Note t: E must be used to clock in the address sequence for the Software STORE and RECALL cycles.
q,r,t
SOFTWARE STORE/RECALL CYCLE
28
AVAV
28
AVAV
t
t
ADDRESS
E
ADDRESS #1
ADDRESS #2
ADDRESS #6
30
AVELN
32
31
ELEHN
t
t
EHAXN
t
23
STORE
22
t
t
RECALL
29
t
ELQZ
HIGH IMPEDANCE
DQ(Data Out)
VALID
VALID
4-58