STK12C68-M
SRAM MEMORY OPERATION
d
(V = 5.0V ± 10%)
CC
READ CYCLES #1 & #2
SYMBOLS
NO.
STK12C68-40M
STK12C68-45M
STK12C68-55M
UNITS
PARAMETER
#1, #2
Alt.
MIN
MAX
MIN
MAX
MIN
MAX
1
2
t
t
Chip Enable Access Time
40
45
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ELQV
AVAV
AVQV
GLQV
AXQX
ELQX
EHQZ
GLQX
ACS
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time
40
45
55
RC
g
3
t
Address Access Time
40
20
45
25
55
35
AA
4
t
Output Enable to Data Valid
Output Hold After Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
OE
5
t
5
5
5
5
5
5
OH
6
t
LZ
h
7
t
17
17
35
20
20
45
25
25
55
HZ
8
t
0
0
0
0
0
0
OLZ
h
9
t
GHQZ
OHZ
e
10
11
t
ELICCH
EHICCL
PA
c,e
t
PS
Note c: Bringing E ≥V will not produce standby currents until any nonvolatile cycle in progress has timed out. See MODE SELECTION table.
IH
Note e: Parameter guaranteed but not tested.
Note f: For READ CYCLE #1 and #2, W is high for entire cycle.
Note g: Device is continuously selected with E low and G low.
Note h: Measured ± 200mV from steady state output voltage.
f,g
READ CYCLE #1
2
AVAV
t
ADDRESS
3
t
AVQV
5
t
AXQX
DQ (Data Out)
DATA VALID
f
READ CYCLE #2
2
AVAV
t
ADDRESS
E
1
ELQV
t
11
EHICCL
t
6
ELQX
t
7
t
4
EHQZ
t
GLQV
G
8
9
t
t
GLQX
GHQZ
DQ (Data Out)
DATA VALID
10
ELICCH
t
ACTIVE
I
STANDBY
CC
4-55