STK12C68-M
d
WRITE CYCLES #1 & #2
(V = 5.0V ± 10%)
CC
SYMBOLS
NO.
STK12C68-40M
STK12C68-45M
STK12C68-55M
UNITS
PARAMETER
#1
#2
Alt.
MIN
MAX
MIN
MAX
MIN
MAX
12
13
14
15
16
17
18
19
20
21
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
35
30
30
18
0
45
35
35
20
0
55
45
45
25
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
AVAV
WLEH
ELEH
DVEH
EHDX
AVEH
AVEL
EHAX
WC
WP
CW
DW
DH
t
t
t
t
t
t
t
t
t
t
Write Pulse Width
WLWH
t
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold After End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold After End of Write
Write Enable to Output Disable
Output Active After End of Write
ELWH
t
DVWH
t
WHDX
t
30
0
35
0
45
0
AVWH
AW
AS
t
AVWL
t
0
0
0
WHAX
WR
WZ
OW
h,j
t
17
20
25
WLQZ
t
5
5
5
WHQX
Note h: Measured ±200mV from steady state output voltage.
Note i: E or W must be ≥ V during address transitions.
IH
Note j: If W is low when E goes low, the outputs remain in the high impedance state.
i
WRITE CYCLE #1: W CONTROLLED
12
AVAV
t
ADDRESS
14
ELWH
19
t
t
WHAX
E
17
t
AVWH
18
AVWL
13
WLWH
t
t
W
15
DVWH
16
WHDX
t
t
DATA IN
DATA VALID
20
WLQZ
21
t
t
WHQX
HIGH IMPEDANCE
PREVIOUS DATA
DATA OUT
i
WRITE CYCLE #2: E CONTROLLED
12
AVAV
t
ADDRESS
18
AVEL
14
ELEH
19
EHAX
t
t
t
E
17
AVEH
t
13
WLEH
t
W
DATA IN
15
DVEH
16
t
t
EHDX
DATA VALID
HIGH IMPEDANCE
DATA OUT
4-56