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STK12C68-5C55M PDF预览

STK12C68-5C55M

更新时间: 2024-01-10 12:29:05
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器
页数 文件大小 规格书
18页 575K
描述
64 Kbit (8K x 8) AutoStore nvSRAM

STK12C68-5C55M 技术参数

是否Rohs认证: 不符合生命周期:Transferred
包装说明:WDIP, DIP28,.3Reach Compliance Code:unknown
ECCN代码:3A001.A.2.CHTS代码:8542.32.00.41
风险等级:8.66Is Samacsys:N
最长访问时间:35 ns其他特性:RETENTION/ENDURANCE = 10 YEARS/100000 CYCLES
JESD-30 代码:R-CDIP-T28JESD-609代码:e0
长度:35.56 mm内存密度:65536 bit
内存集成电路类型:NON-VOLATILE SRAM内存宽度:8
功能数量:1端口数量:1
端子数量:28字数:8192 words
字数代码:8000工作模式:ASYNCHRONOUS
最高工作温度:125 °C最低工作温度:-55 °C
组织:8KX8输出特性:3-STATE
可输出:YES封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:WDIP封装等效代码:DIP28,.3
封装形状:RECTANGULAR封装形式:IN-LINE, WINDOW
并行/串行:PARALLEL电源:5 V
认证状态:Not Qualified筛选级别:38535Q/M;38534H;883B
座面最大高度:4.14 mm最大待机电流:0.004 A
子类别:SRAMs最大压摆率:0.075 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:NO
技术:CMOS温度等级:MILITARY
端子面层:Tin/Lead (Sn85Pb15)端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
宽度:7.62 mmBase Number Matches:1

STK12C68-5C55M 数据手册

 浏览型号STK12C68-5C55M的Datasheet PDF文件第2页浏览型号STK12C68-5C55M的Datasheet PDF文件第3页浏览型号STK12C68-5C55M的Datasheet PDF文件第4页浏览型号STK12C68-5C55M的Datasheet PDF文件第5页浏览型号STK12C68-5C55M的Datasheet PDF文件第6页浏览型号STK12C68-5C55M的Datasheet PDF文件第7页 
STK12C68-5 (SMD5962-94599)  
64 Kbit (8K x 8) AutoStore nvSRAM  
Features  
Functional Description  
35 ns and 55 ns access times  
The Cypress STK12C68-5 is a fast static RAM with a nonvol-  
atile element in each memory cell. The embedded nonvolatile  
Hands off automatic STORE on power down with external  
68 µF capacitor  
elements incorporate QuantumTrap technology producing the  
world’s most reliable nonvolatile memory. The SRAM provides  
unlimited read and write cycles, while independent nonvolatile  
data resides in the highly reliable QuantumTrap cell. Data  
transfers from the SRAM to the nonvolatile elements (the  
STORE operation) takes place automatically at power down.  
On power up, data is restored to the SRAM (the RECALL  
operation) from the nonvolatile memory. Both the STORE and  
RECALL operations are also available under software control.  
A hardware STORE is initiated with the HSB pin.  
STORE to QuantumTrap™ nonvolatile elements is initiated  
by software, hardware, or AutoStore™ on power down  
RECALL to SRAM initiated by software or power up  
Unlimited Read, Write, and Recall cycles  
1,000,000 STORE cycles to QuantumTrap  
100 year data retention to QuantumTrap  
Single 5V+10% operation  
Military temperature  
28-pin (300mil) CDIP and 28-pad LCC packages  
Logic Block Diagram  
V
V
CAP  
CC  
Quantum Trap  
128 X 512  
A5  
POWER  
STORE  
CONTROL  
A6  
A7  
RECALL  
STORE/  
RECALL  
CONTROL  
STATIC RAM  
ARRAY  
128 X 512  
A8  
HSB  
A9  
A11  
A12  
SOFTWARE  
DETECT  
A0 -A12  
DQ0  
COLUMN I/O  
DQ1  
DQ2  
DQ3  
COLUMN DEC  
DQ4  
DQ5  
A0  
A4  
A10  
A1  
A3  
A2  
DQ6  
DQ7  
OE  
CE  
WE  
Cypress Semiconductor Corporation  
Document Number: 001-51026 Rev. **  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised March 02, 2009  
[+] Feedback  

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