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STK12C68-40M PDF预览

STK12C68-40M

更新时间： 2022-12-12 22:00:39
品牌 Logo 应用领域
其他 - ETC 存储静态存储器
页数 文件大小 规格书
10页 74K
描述
CMOS NV SRAM 8K X 8 AUTOSTORE NONVOLATILE STATIC RAM

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STK12C68-40M 数据手册

 浏览型号STK12C68-40M的Datasheet PDF文件第2页浏览型号STK12C68-40M的Datasheet PDF文件第3页浏览型号STK12C68-40M的Datasheet PDF文件第4页浏览型号STK12C68-40M的Datasheet PDF文件第6页浏览型号STK12C68-40M的Datasheet PDF文件第7页浏览型号STK12C68-40M的Datasheet PDF文件第8页 
STK12C68-M  
NONVOLATILE MEMORY OPERATION  
MODE SELECTION  
E
W
HSB  
A
- A (hex)  
0
MODE  
I/O  
POWER  
NOTES  
12  
H
L
L
L
X
H
L
H
H
H
H
X
Not Selected  
Read SRAM  
Output High Z  
Output Data  
Input Data  
Standby  
Active  
Active  
Active  
X
l
X
Write SRAM  
H
0000  
1555  
0AAA  
1FFF  
10F0  
0F0F  
0000  
1555  
0AAA  
1FFF  
10F0  
0F0E  
X
Read SRAM  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Output High Z  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Output High Z  
Output High Z  
k,l  
k,l  
k,l  
k,l  
k,l  
k
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Nonvolatile STORE  
Read SRAM  
L
H
H
Active  
k,l  
k,l  
k,l  
k,l  
k,l  
k
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Nonvolatile RECALL  
STORE/Inhibit  
X
X
L
I
/Standby  
m
CC  
2
Note k: The six consecutive addresses must be in order listed - (0000, 1555, 0AAA, 1FFF, 10F0, 0F0F) for a STORE cycle or (0000, 1555, 0AAA, 1FFF, 10F0,  
0F0E) for a RECALL cycle. W must be high during all six consecutive cycles. See STORE cycle and RECALL cycle tables and diagrams for further details.  
Note l: I/O state assumes that G ≤ V . Activation of nonvolatile cycles does not depend on the state of G.  
IL  
Note m: HSB initiated STORE operation actually occurs only if a WRITE has been done since last STORE operation. After the STORE (if any) completes, the  
part will go into standby mode inhibiting all operation until HSB rises.  
HARDWARE STORE /RECALL  
SYMBOLS  
NO.  
PARAMETER  
MIN  
MAX  
UNITS  
NOTES  
22  
23  
24  
25  
26  
t
t
t
t
t
RECALL Cycle Duration  
STORE Cycle Duration  
HSB Low to Inhibit On  
20  
10  
µs  
ms  
µs  
ns  
ns  
V
Note o  
RECALL  
STORE  
t
V
≥ 4.5V  
CC  
HLHH  
t
1
DELAY  
HLQZ  
t
HSB High to Inhibit Off  
External STORE Pulse Width  
Low Voltage Trigger Level  
HSB Output Low Current  
HSB Output High Current  
300  
4.5  
60  
Note e  
Note e  
RECOVER  
ASSERT  
HHQX  
t
250  
4.0  
3
HLHX  
V
I
SWITCH  
mA  
µA  
HSB = V , Note e, n  
OL  
HSB_OL  
HSB_OH  
I
5
HSB = V , Note e, n  
IL  
Note e: These parameters guaranteed but not tested.  
Note n: HSB is an I/O that has a weak internal pullup; it is basically an open drain output. It is meant to allow up to 32 STK12C68-Ms to be ganged together for  
simultaneous storing. Do not use HSB to pullup any external circuitry other than other STK12C68-M HSB pins.  
Note o: A RECALL cycle is initiated automatically at power up when V exceeds V  
CC  
. t  
is measured from the point at which V exceeds 4.5V.  
CC  
SWITCH RECALL  
HARDWARE STORE /RECALL  
V
SWITCH  
V
26  
ASSERT  
CAP  
24  
DELAY  
t
t
HSB  
W
22  
RECALL  
24  
DELAY  
25  
t
t
t
RECOVER  
RECALL  
STORE  
23  
STORE  
23  
STORE  
23  
t
t
t
STORE  
SRAM  
Inhibit  
Power Up RECALL Brown Out RECALL  
Power Down STORE  
HSB Initiated STORE  
Software STORE  
4-57  
12345678...10

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