STK12C68-M
EEPROMcells. Thenonvolatiledatacanberecalledan connected together. Each chip contains a small inter-
unlimited number of times.
nalcurrentsourcetopullHSBHIGH whenitisnotbeing
driven low. To decrease the sensitivity of this signal to
noise generated on the PC board, it may optionally be
AUTOMATIC RECALL
During power up, or after any low power condition
pulled to V
via an external resistor with a value
CCX
such that the combined load of the resistor and all
parallel chip connections does not exceed I at
(V
< V
), when V
exceeds the sense
CAP
SWITCH
CAP
voltage of V
, a RECALL cycle will automatically
HSB_OL
SWITCH
V
V
. Do not connect this or any other pull-up to the
be initiated. After the initiation of this automatic RE-
CALL, if V falls below V , then another RE-
CALL operation will be performed whenever V
OL
node.
CAP
CAP
SWITCH
CAP
If HSB is to be connected to external circuits other than
otherSTK12C68-Ms,anexternalpull-upresistorshould
be used.
again rises above V
.
SWITCH
If the STK12C68-M is in a WRITE state at the end of
power-up RECALL, the SRAM data will be corrupted.
To help avoid this situation, a 10K Ohm resistor should
During any STORE operation, regardless of how it was
initiated, the STK12C68-M will continue to drive the
HSB pin low, releasing it only when the STORE is
complete. Upon completion of a STORE operation, the
part will be disabled until HSB actually goes HIGH.
be connected between W and system V
.
CC
HARDWARE PROTECT
The STK12C68-M offers hardware protection against
inadvertent STORE operation during low voltage
AUTOMATIC STORE OPERATION
During normal operation, the STK12C68-M will draw
conditions. When V
< V
all externally
SWITCH,
CAP
initiated STORE operations will be inhibited.
current from V
to charge up a capacitor connected
CCX
to the V
pin. This stored charge will be used by the
HSB OPERATION
CAP
chip to perform a single STORE operation. After power
up, when the voltage on the V pin drops below
The Hardware Store Busy pin (HSB) is an open drain
circuit acting as both input and output to perform two
different functions. When driven low by the internal
chip circuitry it indicates that a STORE operation (initi-
ated via any means) is in progress within the chip.
When driven low by external circuitry for longer than
CAP
V
V
, the part will automatically disconnect the
SWITCH
CAP
pin from V
and initiate a STORE operation.
CCX
Figure 1 shows the proper connection of capacitors for
automaticstoreoperation. Thechargestoragecapaci-
tor should have a capacity of at least 100µF (± 20%) at
6V. Each STK12C68-M must have its own 100µF
capacitor. Each STK12C68-M must have a high
quality, high frequency bypass capacitor of 0.1µF
t
, the chip will conditionally initiate a STORE
ASSERT
operation after t
.
DELAY
READ and WRITE operations that are in progress when
HSB is driven low (either by internal or external cir-
cuitry) will be allowed to complete before the STORE
operation is performed, in the following manner. After
HSB goes low, the part will continue normal SRAM
connected between V
traces that are as short as possible.
and V , using leads and
CAP
SS
If the AutoStore™ function is not required, then V
should be tied directly to the power supply and V
operations for t
. During t
, a transition on
CAP
CCX
DELAY
DELAY
any address or control signal will terminate SRAM
operation and cause the STORE to commence. Note
that if an SRAM write is attempted after HSB has been
forced low, the write will not occur and the STORE
operation will begin immediately.
should be tied to ground. In this mode, STORE opera-
tions may be triggered through software control or the
HSB pin. In either event, V
have a proper bypass capacitor connected to it.
(Pin 1) must always
CAP
In order to prevent unneededSTORE operations, auto-
matic STOREs as well as those initiated by externally
driving HSB LOW will be ignored unless at least one
Hardware-Store-Busy (HSB) is a high speed, low drive
capability bi-directional control line. In order to allow a
bankofSTK12C68-MstoperformsynchronizedSTORE
functions, the HSB pin from a number of chips may be
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