Datasheet > STK12C68-40M

STK12C68-40M

更新时间： 2022-12-12 22:00:39

品牌	Logo	应用领域
其他 - ETC		存储静态存储器
页数	文件大小	规格书
10页	74K
描述
CMOS NV SRAM 8K X 8 AUTOSTORE NONVOLATILE STATIC RAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

STK12C68-40M 数据手册

STK12C68-M

WRITE operationhastakenplacesincethemostrecent access cycle time is longer than 55ns. Figure 2 below

STORE cycle. NotethatifHSBisdrivenlowviaexternal shows the relationship between I and access times

circuitry and no WRITEs have taken place, the part will for READ cycles. All remaining inputs are assumed to

still be disabled until HSB is allowed to return HIGH. cycle, and current consumption is given for all inputs at

SoftwareinitiatedSTORE cyclesareperformedregard- CMOS orTTLlevels. Figure3showsthesamerelation-

less of whether or not a WRITE operation has taken ship for WRITE cycles. When E is HIGH, the chip

place.

consumes only standby currents, and these plots do

not apply.

PREVENTING AUTOMATIC STORES

The cycle time used in Figure 2 corresponds to the

length of time from the later of the last address transi-

tion or E goingLOW to the earlier of E going HIGH or the

next address transition. W is assumed to be HIGH,

while the state of G does not matter. Additional current

is consumed when the address lines change state

while E is asserted. The cycle time used in Figure 3

corresponds to the length of time from the later of W or

E going LOW to the earlier of W or E going HIGH.

The AutoStore™ function can be disabled on the fly by

holding HSB HIGH with a driver capable of sourcing

15mA at a VOH of at least 2.2V as it will have to

overpower the internal pull-down device that drives

HSB low for 50ns at the onset of an AutoStore™.

When the STK12C68-M is connected for

AutoStore™operation(systemV connectedtoV

CCX

and a 100uF capacitor on V

) and V

crosses

CAP

on the way down, the STK12C68 will attempt

SWITCH

topullHSB LOW;ifHSBdoesn'tactuallygetbelowV ,

Theoverallaveragecurrentdrawnbythepartdepends

on the following items: 1) CMOS or TTL input levels; 2)

the time during which the chip is disabled (E HIGH); 3)

the cycle time for accesses (E LOW); 4) the ratio of

reads to writes; 5) the operating temperature; 6) the

the part will stop trying to pull HSB LOW and abort the

AutoStore™attempt.

LOW AVERAGE ACTIVE POWER

The STK12C68-M has been designed to draw signifi-

cantlylesspowerwhenEisLOW (chipenabled)butthe

level; and 7) output load.

CAP

CCX

Power

Supply

100

10K Ohms

(optional)

HSB

100uF

± 20%

0.1uF

Bypass

nvSRAM

TTL

CMOS

150 200

CMOS

100

150

200

Cycle Time (ns)

Figure 2

(Max) Reads

Figure 3

(Max) Writes

Figure 1

Schematic Diagram

Note: Typical at 25° C

4-61

1...6 7 8910

中文翻译

下载PDF

与STK12C68-40M相关器件

型号	品牌	描述	获取价格	数据表
STK12C68-45M	ETC	CMOS NV SRAM 8K X 8 AUTOSTORE NONVOLATILE STATIC RAM	获取价格
STK12C68-5	CYPRESS	64 Kbit (8K x 8) AutoStore nvSRAM	获取价格
STK12C68-55M	ETC	CMOS NV SRAM 8K X 8 AUTOSTORE NONVOLATILE STATIC RAM	获取价格
STK12C68-5C25	ETC	8K x 8 AutoStore⑩ nvSRAM QuantumTrap⑩ CMOS No	获取价格
STK12C68-5C25I	ETC	8K x 8 AutoStore⑩ nvSRAM QuantumTrap⑩ CMOS No	获取价格
STK12C68-5C25M	ETC	8K x 8 AutoStore⑩ nvSRAM QuantumTrap⑩ CMOS No	获取价格