Datasheet > STD421S

STD421S

更新时间： 2024-11-24 06:14:35

品牌	Logo	应用领域
三合微科 - SAMHOP		晶体晶体管
页数	文件大小	规格书
8页	498K
描述
P -Channel Logic Level E nhancement Mode F ield E ffect Transistor

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数据手册

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STD421S 数据手册

S TU/D421S

S amHop Microelectronics C orp.

Aug.20,2006

P -C hannel Logic Level E nhancement Mode Field E ffect Transistor

FE ATUR E S

PR ODUCT S UMMAR Y

R DS (ON) ( m

Ω

) Max

VDS S

S uper high dense cell design for low R DS (ON).

R ugged and reliable.

45 @ VG S = -10V

60 @ VG S = -4.5V

-10A

-40V

TO-252 and TO-251 P ackage.

S TU S E R IE S

TO-252AA(D-P AK)

S TD S E R IE S

TO-251(l-P AK)

AB S OL UTE MAXIMUM R ATING S

(T =25 C unles s otherwis e noted)

Unit

Limit

P arameter

S ymbol

Drain-S ource Voltage

G S

-40

G ate-S ource Voltage

25 C

-10

Drain C urrent-C ontinuous @ Ta

70 C

-8.3

-P ulsed ^b

-50

-10

Drain-S ource Diode Forward C urrent ^a

Ta= 25 C

Maximum P ower Dissipation ^a

Ta=70 C

Operating J unction and S torage

Temperature R ange

-55 to 175

TJ , TS TG

THE R MAL C HAR AC TE R IS TIC S

Thermal R esistance, J unction-to-C ase

C/W

J C

J A

Thermal R esistance, J unction-to-Ambient

12 3 4 5 6 7 8

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