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SPAK321TFC240D PDF预览

SPAK321TFC240D

更新时间: 2024-11-13 21:09:39
品牌 Logo 应用领域
恩智浦 - NXP 时钟外围集成电路
页数 文件大小 规格书
88页 1195K
描述
24-BIT, 240MHz, OTHER DSP, PBGA196, 15 X 15 MM, 1 MM PITCH, MOLDED ARRAY PROCESS, BGA-196

SPAK321TFC240D 技术参数

生命周期:Obsolete零件包装代码:BGA
包装说明:BGA,针数:196
Reach Compliance Code:unknownECCN代码:3A001.A.3
HTS代码:8542.31.00.01风险等级:5.59
其他特性:ALSO REQUIRES 3.3V SUPPLY地址总线宽度:18
桶式移位器:YES边界扫描:YES
最大时钟频率:240 MHz外部数据总线宽度:24
格式:FIXED POINT内部总线架构:MULTIPLE
JESD-30 代码:S-PBGA-B196长度:15 mm
低功率模式:YES端子数量:196
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装形状:SQUARE封装形式:GRID ARRAY
认证状态:Not Qualified座面最大高度:2.43 mm
最大供电电压:1.7 V最小供电电压:1.5 V
标称供电电压:1.6 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM宽度:15 mm
uPs/uCs/外围集成电路类型:DIGITAL SIGNAL PROCESSOR, OTHERBase Number Matches:1

SPAK321TFC240D 数据手册

 浏览型号SPAK321TFC240D的Datasheet PDF文件第2页浏览型号SPAK321TFC240D的Datasheet PDF文件第3页浏览型号SPAK321TFC240D的Datasheet PDF文件第4页浏览型号SPAK321TFC240D的Datasheet PDF文件第5页浏览型号SPAK321TFC240D的Datasheet PDF文件第6页浏览型号SPAK321TFC240D的Datasheet PDF文件第7页 
Freescale Semiconductor, Inc.  
Technical Data  
Advance Information  
DSP56321T/D  
Rev. 2, 10/2002  
24-Bit Digital Signal  
Processor  
3
16  
6
6
Memory Expansion Area  
Program  
RAM  
Triple  
Timer  
32 K × 24 bits  
SCI  
HI08  
ESSI  
EFCOP  
or  
X Data  
RAM  
Y Data  
RAM  
31 K × 24 bits  
and  
Instruction  
80 K × 24 bits 80 K × 24 bits  
Cache  
1024 × 24 bits  
Peripheral  
The DSP56321T is a  
member of the  
Expansion Area  
YAB  
Address  
DSP56300 Digital  
Signal Processor (DSP)  
family intended for  
applications requiring a  
large amount of  
on-device memory. The  
on-board EFCOP can  
accelerate general  
filtering applications,  
such as  
External  
Address  
Bus  
XAB  
PAB  
DAB  
18  
Generation  
Unit  
Address  
Switch  
Six Channel  
DMA Unit  
External  
Bus  
24-Bit  
DSP56300  
Core  
13  
Interface  
and  
Bootstrap  
ROM  
Control  
I - Cache  
Control  
DDB  
YDB  
XDB  
PDB  
GDB  
External  
Data  
Internal  
Data  
24  
Bus  
Bus  
Switch  
Data  
Switch  
Power  
echo-cancellation,  
correlation, and  
general-purpose  
Management  
Data ALU  
5
Program  
Interrupt  
Controller  
Program  
Decode  
Controller  
Program  
Address  
Generator  
Clock  
Generator  
+
24 × 24 56 56-bit MAC  
JTAG  
PLL  
Two 56-bit Accumulators  
56-bit Barrel Shifter  
OnCE™  
convolution-based  
algorithms. By operating  
in parallel with the core,  
the EFCOP provides  
overall enhanced  
DE  
EXTAL  
XTAL  
RESET  
PINIT/NMI  
MODA/IRQA  
MODB/IRQB  
MODC/IRQC  
MODD/IRQD  
PCAP  
Figure 1. DSP56321T Block Diagram  
performance and signal  
quality with no impact  
on channel throughput  
or total channel support.  
The Motorola DSP56321T supports networking,  
security encryption, and home entertainment  
applications using a high- performance,  
single-clock-cycle-per- instruction engine  
(DSP56000 code-compatible), a barrel shifter,  
24-bit addressing, an instruction cache, and a  
six-channel direct memory access (DMA)  
controller (see Figure 1).  
The DSP5321T offers 220/240 MMACS  
performance, attaining 440/480 MMACS when the  
EFCOP is in use, It operates with an internal  
220/240 MHz clock, using a 1.6 volt core and  
independent 3.3 volt input/output (I/O) power.  
This device is pin- compatible with the Motorola  
DSP56303, DSP56L307, DSP56309, and  
DSP56311.  
Note: This document contains information on a new product. Specifications and information herein are subject to change without notice.  
For More Information On This Product,  
Go to: www.freescale.com  
 
 

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