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SPAKDSP301VF100 PDF预览

SPAKDSP301VF100

更新时间: 2024-11-13 21:22:11
品牌 Logo 应用领域
摩托罗拉 - MOTOROLA /
页数 文件大小 规格书
132页 1117K
描述
Digital Signal Processor, 24-Ext Bit, 100MHz, CMOS, PBGA252, 21 X 21 MM, 1.27 MM PITCH, MOLDED ARRAY PROCESS, BGA-252

SPAKDSP301VF100 技术参数

生命周期:Transferred包装说明:BGA,
Reach Compliance Code:unknownECCN代码:3A001.A.3
HTS代码:8542.31.00.01风险等级:5.76
地址总线宽度:24桶式移位器:YES
边界扫描:YES最大时钟频率:100 MHz
外部数据总线宽度:24格式:FIXED POINT
内部总线架构:MULTIPLEJESD-30 代码:S-PBGA-B252
长度:21 mm低功率模式:YES
端子数量:252封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装形状:SQUARE
封装形式:GRID ARRAY认证状态:Not Qualified
座面最大高度:1.9 mm最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
端子形式:BALL端子节距:1.27 mm
端子位置:BOTTOM宽度:21 mm
uPs/uCs/外围集成电路类型:DIGITAL SIGNAL PROCESSOR, OTHERBase Number Matches:1

SPAKDSP301VF100 数据手册

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Technical Data  
DSP56301/D  
Rev. 6, 11/2002  
24-Bit Digital Signal  
Processor  
52  
6
6
3
Memory Expansion Area  
Y Data  
RAM  
2048 × 24  
bits  
(Default)  
X Data  
RAM  
2048 × 24  
bits  
(Default)  
Program  
RAM  
4096 × 24 bits  
Host  
Interface  
Triple  
Timer  
ESSI  
SCI  
(Default)  
Peripheral  
Expansion Area  
24  
14  
The DSP56301 is  
intended for  
general-purpose  
digital signal  
External  
Address  
Bus  
Address  
XAB  
PAB  
DAB  
Generator  
Unit  
Switch  
Six-Channel  
DMA Unit  
External  
Bus  
24-Bit  
DSP56300  
Core  
Interface  
and  
Boot-  
strap  
ROM  
processing,  
I-Cache  
Control  
particularly in  
multimedia and  
telecommunication  
applications, such as  
video conferencing  
and cellular  
DDB  
YDB  
XDB  
PDB  
GDB  
24  
External  
Data  
Bus  
Internal  
Data  
Bus  
Switch  
Power  
EXTAL  
XTAL  
Management  
telephony.  
Clock  
Data ALU  
Program  
Program  
Decode  
Controller  
Program  
6
+
24 × 24 56 56-bit MAC  
Two 56-bit Accumulators  
56-bit Barrel Shifter  
JTAG  
Interrupt  
Address  
PLL  
2
Controller  
Generator  
OnCE™  
MODD/IRQD  
MODC/IRQC  
MODB/IRQB  
MODA/IRQA  
RESET  
PINIT/NMI  
Figure 1. DSP56301 Block Diagram  
The DSP56301 is a member of the DSP56300  
core family of programmable CMOS Digital  
Signal Processors (DSPs). This family uses a  
high-performance, single clock cycle per  
instruction engine providing a twofold  
performance increase over Motorolas popular  
DSP56000 core family while retaining code  
compatibility.  
Significant architectural features of the DSP56300  
core family include a barrel shifter, 24-bit  
addressing, instruction cache, and DMA. The  
DSP56301 offers 80/100 MIPS using an internal  
80/100 MHz clock at 3.0–3.6 volts. The DSP56300  
core family offers a rich instruction set and low  
power dissipation, as well as increasing levels of  
speed and power, enabling wireless,  
telecommunications, and multimedia products.  
 

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